The Xilinx Alliance 3.3i software Section C Synplicity has now generated a top-level description of your System Generator design. We must now pass the EDIF netlists to the Xilinx Place and Route tools. The Xilinx Alliance 3.3i software Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Start a New Project 1 Select File -> New Project 2 Browse to the directory to where you told Synplicity to write the EDIF files. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Select The Right EDIF file! Notice how there are several EDIF files in your Synplicity directory. The *.edf file should be the EDIF file that Synplicity produced for the top level of the System Generator design, (in this case, rgb2ycbcr_full_mult.edf) 1 2 Select “OPEN.” The *.edn files are what the CORE Generator wrote out for those modules in your System Generator design that map to Xilinx CORE Generator cores. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Select The Right EDIF file! 1 Click on “OK” and wait while the software sets itself up. This involves writing new files and setting up a directory structure that defaults to the name xproj. Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Click on “OK” again You can explore the Tutorials to find out what all these buttons mean, but it’s fine to just click on “OK” again. 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - VERY IMPORTANT STEP You must set your timing constraints if you want to hit a certain speed performance. PAR will only work as hard as it has to. If you do not set it any targets, it will not work hard at all! How does it know what you want? You can use the Constraints editor (Utilities -> Constraints Editor), to set your “PERIOD” constraint, plus much more. (A Timing Constraints training course is currently being designed to more fully explain all of the Constraints Editor options). 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Set PERIOD Constraint 1 Note that it is necessary to run the “TRANSLATE” portion of the Xilinx tool flow before the Constraints Editor can operate. This is done automatically for you; just click on “YES.” Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Observe the Flow Manager 1 Note that the Xilinx Flow Manager automatically pops up, and starts the TRANSLATE stage of the flow. NGDBuild is invoked, and a “STOP” sign is symbolically placed in the flow to denote that the flow will stop at this point. Once NGDBuild has finished, the next thing you will see is the Constraints Editor window pop up... Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Set The Clock Period 1 Double-click on this window. 3 Set the units to MHz or ns. 2 Set this box to your target speed (MHz or ns). 4 Click “OK” to close the Period Box Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Close The Editor 1 Close the Constraints Editor (File ->Close). 2 Select “Yes.” Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Rerun the Translate step 1 Select “Yes.” NGDBuild needs to be run again so that the newly created timespecs can be annotated into the User Constraints File (UCF), design.ucf Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Run Translate & MAP Note that the flow manager stops after MAP; this allows you to do a check point timing verification to make sure that your LUT delays do not exceed your minimum path propagation delay. If they do, then it is a waste of time for PAR to try to place and route the design. 2 This time, the Xilinx Flow manager will automatically take the design through the Translate stage with the new timing constraints, then on to the MAP phase to partition the logical design into physical elements (LUTs, FFs, and BRAMs). 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Run Translate & MAP To run the flow beyond the stop sign, you must click on the “stop” icon here. 1 Now select Place&Route and click “OK.” 2 The “Stop After” box will go away and you can select the “continue” button. 3 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - PAR Successfully Finished After PAR completes successfully, close or iconize the Flow Manager, and return to the Xilinx Design Manager. 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

The Design Flow has now completed. We must analyze the design to confirm that it met our timing constraints; we might also have a look at the Floorplan of the final design (not necessary, but it can be useful). Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Timing Analysis Use the Static Timing Analyzer (TRACE program), to verify that the design will operate at the required 27MHz. 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Timing Analyzer When this blank window pops up, simply select this icon, then click “OK” to analyze it against your timing constraints. 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - Timing Analyzer Note that there are no red lines in the left- hand hierarchy window. This means that all constraints were met. This is also confirmed in the report file shown (i.e., “0 timing errors detected”). 1 Andy Miller © Copyright 2000 Xilinx - All Rights Reserved

Xilinx Flow - View the Floorplan? Note how the cores (RPM’s) have a single colour. 1 (Press your “Page Down” key to end the presentation)