Review In last lecture, done with unsigned and signed number representation. Introduced how to represent real numbers in float format.

5/3/2019 Biased Notation The most negative exponent will be represented as 00…00 and the most positive as 111…11 That is, we need to subtract the bias from the corresponding unassigned value The value of an IEEE 754 single precision is 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 s exponent fraction 1 bit 8 bits 23 bits 5/3/2019 CDA3100 CDA3100

5/3/2019 Example 101.11two= 22 + 20 + 2-1 + 2-2 = 5.75 The normalized binary number will be 1.011122 = 1.01112(129-127) So the exponent is 129ten = 10000001 As a hexadecimal number, the representation is 0x40B80000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5/3/2019 CDA3100 CDA3100

IEEE 754 Double Precision It uses 64 bits (two 32-bit words) 5/3/2019 IEEE 754 Double Precision It uses 64 bits (two 32-bit words) 1 bit for the sign 11 bits for the exponent 52 bits for the fraction 1023 as the bias 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 s Exponent fraction 1 bit 11 bits 20 bits Fraction (continued) 32 bits 5/3/2019 CDA3100 CDA3100

Example (Double Precision) 5/3/2019 Example (Double Precision) 101.11two= 22 + 20 + 2-1 + 2-2 = 5.75 The normalized binary number will be 1.011122 = 1.01112(1025-1023) So the exponent is 1025ten = 10000000001two As a hexadecimal number, the representation is 0x4017 0000 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5/3/2019 CDA3100 CDA3100

floating-point number 5/3/2019 Special Cases Single precision Double precision Object represented Exponent Fraction nonzero denormalized number 1-254 anything 1-2046 floating-point number 255 2047  infinity NaN (Not a number) Denormalized If the exponent is all 0s, but the fraction is non-zero (else it would be interpreted as zero), then the value is a denormalized number, which does not have an assumed leading 1 before the binary point. Thus, this represents a number (-1)s × 0.f × 2-126, where s is the sign bit and f is the fraction. For double precision, denormalized numbers are of the form (-1)s × 0.f × 2-1022. From this you can interpret zero as a special type of denormalized number. Denormalized numbers A number is denormalized if the exponent field contains all 0's and the fraction field does not contain all 0's. Thus denormalized single-precision numbers can be in the range (plus or minus) to inclusive. Denormalized double-precision numbers can be in the range (plus or minus) to inclusive. Denormalized extended-precision numbers do not have a 1 bit in position 63. Therefore, it stores numbers in the range (plus or minus) to inclusive. Both positive and negative zero values exist, but they are treated the same during floating point calculations. CDA3100 5/3/2019 CDA3100

Ranges for IEEE 754 Single Precision 5/3/2019 Ranges for IEEE 754 Single Precision Largest positive number Smallest positive number Floating-point number Denormalized number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5/3/2019 CDA3100 CDA3100

Comments on Overflow and Underflow 5/3/2019 Comments on Overflow and Underflow Overflow (and underflow also for floating numbers) happens when a number is outside the range of a particular representation For example, by using 8-bit two’s complement representation, we can only represent a number between -128 and 127 If a number is smaller than -128, it will cause overflow If a number is larger than 127, it will cause overflow also Note that arithmetic operations can result in overflow 5/3/2019 CDA3100 CDA3100

Ranges for IEEE 754 Single Precision 5/3/2019 Ranges for IEEE 754 Single Precision Largest positive number Smallest positive number Floating-point number Denormalized number Overflow and underflow Overflow if the exponent is too large to be represented Underflow if the exponent is too small to be represented 5/3/2019 CDA3100 CDA3100

Ranges for IEEE 754 Double Precision 5/3/2019 Ranges for IEEE 754 Double Precision Largest positive number Smallest positive number Floating-point number Denormalized number 5/3/2019 CDA3100 CDA3100

Range for Intel’s 80-bit Format 5/3/2019 Range for Intel’s 80-bit Format Intel’s IA-32 internally uses a 80-bit floating point (extended precision representation) It includes a sign bit, a 16-bit exponent, and 63-bit significant (64-bit if the implied 1 is also included) The bias is 32767 What is the largest positive number? What is the smallest positive number? 5/3/2019 CDA3100 CDA3100

5/3/2019 Endianness Byte ordering  How a multiple byte data word stored in memory Endianness (from Gulliver’s Travels) Big endian Most significant byte of a multi-byte word is stored at the lowest memory address e.g. MIPS, Sun Sparc, PowerPC Little endian Least significant byte of a multi-byte word is stored at the lowest memory address e.g. Intel x86 5/3/2019 CDA3100 CDA3100

Endianness - continued 5/3/2019 Endianness - continued Note that the bit fields depend on the endianness of the machine Bit field direction on little endian machines 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 s exponent fraction 1 bit 8 bits 23 bits Bit field direction on big endian machines 5/3/2019 CDA3100 CDA3100

Meaning of Bit Patterns 5/3/2019 Meaning of Bit Patterns What a bit pattern represents depends what it is for Example, the following bit pattern A two’s complement integer An unsigned integer A single precision floating-point number A MIPS instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5/3/2019 CDA3100 CDA3100

Meaning of Bit Patterns 5/3/2019 Meaning of Bit Patterns What a bit pattern represents depends what it is for Example, the following bit pattern A two’s complement integer An unsigned integer A single precision floating-point A MIPS instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 5/3/2019 CDA3100 CDA3100

Stored Program Concept 5/3/2019 Stored Program Concept 5/3/2019 CDA3100 CDA3100

Stored Program Concept 5/3/2019 Stored Program Concept Programs consist of instructions and data Instructions are also represented as 0’s and 1’s Before a program runs, it will be loaded and stored in memory; it can be read and written just like numbers A program is executed instruction by instruction These apply to all kinds of programs, operating systems, applications, games, and so on 5/3/2019 CDA3100 CDA3100

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5/3/2019 GoogleEarth.exe 5/3/2019 CDA3100 CDA3100

5/3/2019 Linux Kernel 5/3/2019 CDA3100 CDA3100

Instruction Set Architectures 5/3/2019 Instruction Set Architectures An instruction set architecture specifies Instructions Registers Memory access Input/output An instruction set architecture provides an abstraction of the hardware implementation The hardware implementation decides what and how instructions are implemented 5/3/2019 CDA3100 CDA3100

Stored Program Concept 5/3/2019 Stored Program Concept 5/3/2019 CDA3100 CDA3100

Instruction Execution Steps 5/3/2019 Instruction Execution Steps Instruction fetch step Fetch the instruction from memory and compute the address of the next sequential instruction Instruction decode and register fetch step Decode the instruction and read registers Instruction execution Memory access Write back 5/3/2019 CDA3100 CDA3100

Arithmetic Instruction Execution 5/3/2019 Arithmetic Instruction Execution 5/3/2019 CDA3100 CDA3100

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5/3/2019 MIPS ISA There are many different instruction set architectures designed for different applications with different performance/cost tradeoff Including Intel-32, PowerPC, MIPS, ARM …. We focus on MIPS architecture Microprocessor without Interlocked Pipeline Stages A RISC (reduced instruction set computer) architecture In contrast to CISC (complex instruction set computer) Similar to other architectures developed since the 1980's Almost 100 million MIPS processors manufactured in 2002 Used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, … 5/3/2019 CDA3100 CDA3100

Abstract View of MIPS Implementation 5/3/2019 Abstract View of MIPS Implementation 5/3/2019 CDA3100 CDA3100

5/3/2019 MIPS Instruction Set An instruction is a command that hardware understands Instruction set is the vocabulary of commands understood by a given computer It includes arithmetic instructions, memory access instructions, logical operations, instructions for making decisions 5/3/2019 CDA3100 CDA3100

Arithmetic Instructions 5/3/2019 Arithmetic Instructions Each MIPS arithmetic instruction performs only one operation Each one must always have exactly three variables add a, b, c # a = b + c Note that these variables can be the same though If we have a more complex statement, we have to break it into pieces 5/3/2019 CDA3100 CDA3100

Arithmetic Instructions 5/3/2019 Arithmetic Instructions Example f = (g + h) – (i + j) 5/3/2019 CDA3100 CDA3100

Arithmetic Instructions 5/3/2019 Arithmetic Instructions Example f = (g + h) – (i + j) add t0, g, h # temporary variable t0 contains g + h add t1, i, j # temporary variable t1 contains i + j sub f, t0, t1 # f gets t0 – t1 5/3/2019 CDA3100 CDA3100

Operands of Computer Hardware 5/3/2019 Operands of Computer Hardware In C, we can define as many as variables as we need In MIPS, operands for arithmetic operations must be from registers Note: in some architectures (including IA 32), some operands can be from memory directly MIPS has thirty-two 32-bit registers What can we do if we need more variables than the number of the registers we have? 5/3/2019 CDA3100 CDA3100

5/3/2019 MIPS Registers 5/3/2019 CDA3100 CDA3100

Arithmetic Instructions 5/3/2019 Arithmetic Instructions Example f = (g + h) – (i + j) #In MIPS, add can not access variables directly #because they are in memory # Suppose f, g, h, i, and j are in $s0, $s1, $s2, $s3, $s4 respectively add $t0, $s1, $s2 # temporary variable t0 contains g + h add $t1, $s3, $s4 # temporary variable t1 contains i + j sub $s0, $t0, $t1 # f gets t0 – t1 5/3/2019 CDA3100 CDA3100

5/3/2019 Memory Operands Since variables (they are data) are initially in memory, we need to have data transfer instructions Note a program (including data (variables)) is loaded from memory We also need to save the results to memory Also when we need more variables than the number of registers we have, we need to use memory to save the registers that are not used at the moment Data transfer instructions lw (load word) from memory to a register st (store word) from register to memory 5/3/2019 CDA3100 CDA3100

Specifying Memory Address 5/3/2019 Specifying Memory Address Memory is organized as an array of bytes (8 bits) 5/3/2019 CDA3100 CDA3100

Specifying Memory Address 5/3/2019 Specifying Memory Address MIPS uses words (4 bytes) Each word must start at address that are multiples of 4 This is called alignment restriction 5/3/2019 CDA3100 CDA3100

5/3/2019 Example of Endianness Store 0x87654321 at address 0x0000, byte-addressable 5/3/2019 CDA3100 CDA3100

5/3/2019 Example of Endianness Store 0x87654321 at address 0x0000, byte-addressable 5/3/2019 CDA3100 CDA3100

5/3/2019 Using Load and Store Memory address in load and store instructions is specified by a base register and offset This is called base addressing 5/3/2019 CDA3100 CDA3100

5/3/2019 Using Load and Store How to implement the following statement using the MIPS assembly we have so far? Assuming the address of A is in $s3 and the variable h is in $s2 A[12] = h + A[8] 5/3/2019 CDA3100 CDA3100

MIPS Assembly Programs 5/3/2019 MIPS Assembly Programs Consists of MIPS instructions and data Instructions are given in .text segments A MIPS program can have multiple .text segments Data are defined in .data segments using MIPS assembly directives .word, for example, defines the following numbers in successive memory words See Appendix A A.10 (pp. A-45 – A-48) for details 5/3/2019 CDA3100 CDA3100

First MIPS Assembly Program 5/3/2019 First MIPS Assembly Program Compute the sum of first five homework assignment scores The scores are in memory We need to Load the address to a register Load the first two scores Add them Then load third score and add it to the sum and so on 5/3/2019 CDA3100 CDA3100

First MIPS Assembly Program 5/3/2019 First MIPS Assembly Program 5/3/2019 CDA3100 CDA3100

Summary MIPS ISA Stored program concept 5/3/2019 Summary Stored program concept Note that programs are represented using 0’s and 1’s as numbers An instruction set architecture specifies the instructions, registers, and input/output of a computer architecture Instructions are commands that hardware understands MIPS ISA Two types of MIPS instructions so far Arithmetic Operands for arithmetic instructions are restricted Data transfer Load from memory to a register Store a register to memory 5/3/2019 CDA3100 CDA3100