Week 6, Multiplexer & Demultiplexer Introduction to Digital System and Microprocessor Design Inhwan Lee, Youngtaek Oh, Daehyun Ahn (inhwan301, koyt1126, daehyun.ahn)@postech.ac.kr Mar 27, 2018 1/12

Two method to write code Gate Level - Programming with only gates (+) Mostly synthesizable, which means if you pass simulation, it can be hardware. (-) Hard to make complicated hardware. RTL (Register Transfer Level) - Design a source code using abstraction, which models circuits as a flow of data signals between registers and logical operation (&, I) (+) Compilers do translation RTL to gate level (-) Sometimes hard to be a real hardware Last week: Gate Level Coding This week: RTL Coding 2/12

4x1 Multiplexer S0 S1 Y I0 1 I1 I2 I3 2-to-4 Decoder Y = I0S0’S1’+ I1S0S1’ + I2S0’S1 +I3S0S1 3/12

1x4 Demultiplexer S0 S1 D0 D1 D2 D3 I 1 2-to-4 Decoder D0= I S0’S1’ , D1= I S0S1’ , D2= I S0’S1 , D3= I S0 S1 4/12

‘Always’ Block in Verilog - Imperative code that can perform standard data manipulation tasks (if-else, case) - Processes run until they delay for a period of time or wait for a triggering event Syntax always @(condition) begin /*Block of code*/ end 5/12

‘if’ and ‘case’ command in Verilog if command if (expression1) true_statement1; else if (expression2) true_statement2; ... else false_statement; 6/12

‘if’ command example S0 S1 D0 D1 D2 D3 I 1 7/12

‘if’ and ‘case’ command in Verilog case (expression) item_1, … , item_n: statement1; item_n+1, … , item_m: statement2; … default: default_statement; endcase 8/12

‘case’ command example I 1 9/12

‘Assign’ command and conditional operator in Verilog Assign command connects RHS to LHS wire Conditional operator assign a = (expression) ? true_wire_value : false_wire_value ; Equal Expression (in this case, a is reg) always @(*) begin if (expression) a = true_wire_value; else a = false_wire_value; end 10/12

Goal Design 4x1 multiplexer using ‘always’ block and ‘if’ / ‘case’ command Design 1x4 demultiplexer using ‘assign’ command (Don’t use ‘always’) Implement each program into the kit 11/12

Pin Planning FPGA Signal Xilinx BUTTON_SW[0] AD10 BUTTON_SW[1] AC10 AA9 BUTTON_SW[3] Y9 BUTTON_SW[4] Y10 BUTTON_SW[5] AB9 FPGA Signal Xilinx LED_D(0) AB7 LED_D(1) AA7 LED_D(2) AF7 LED_D(3) AC7 LED_D(4) AD6 LED_D(5) AC6 LED_D(6) AF6 LED_D(7) AE6 12/12