© 2014 Synopsys. All rights reserved.1 Wheres my glass slipper? TAU 2014 Nanda Gopal Director R&D, Characterization.

Slides:



Advertisements
Similar presentations
WATERLOO ELECTRICAL AND COMPUTER ENGINEERING 20s: Computer Hardware 1 WATERLOO ELECTRICAL AND COMPUTER ENGINEERING 20s Computer Hardware Department of.
Advertisements

Sheldon Brown, UCSD, Site Director Milton Halem, UMBC Director Yelena Yesha, UMBC Site Director Tom Conte, Georgia Tech Site Director Fundamental Research.
Slide 1 Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed- Signal Circuits by Reusing Early-Stage Data Fa Wang*, Wangyang Zhang*,
Prescriptive Analytics Part I Nick Gonzalez, 2/10/14.
1 © NOKIA Presentation_Name.PPT / / Jukka K. Nurminen OR at Nokia Research Center Jukka K. Nurminen Nokia Research Center
© 2015 Synopsys, Inc. All rights reserved.1 Timing Analysis in a Mixed Signal World TAU Workshop Panel Session Jim Sproch March 12, 2015.
PERFECT Empower Project: Prototype Software Releases PI: Massoud Pedram Co-PIs: Murali Annavaram and Kaushik Roy (Purdue) July 17, 2014.
IC Interconnect Modeling Dr. Paul Van Halen PROBLEM  Resistive, capacitive and inductive effects in circuit interconnect.
1 HW/SW Partitioning Embedded Systems Design. 2 Hardware/Software Codesign “Exploration of the system design space formed by combinations of hardware.
Shadow Configurations: A Network Management Primitive Richard Alimi, Ye Wang, Y. Richard Yang Laboratory of Networked Systems Yale University.
Assignment II Integrated Circuits Design Ping-Hsiu Lee Reagan High School, Houston I. S. D. Deborah Barnett Tidehaven High School, Tidehaven I. S. D. Faculty.
Sheldon Brown, UCSD, Site Director Milton Halem, UMBC Director Yelena Yesha, UMBC Site Director Tom Conte, Georgia Tech Site Director Fundamental Research.
CAD and Design Tools for On- Chip Networks Luca Benini, Mark Hummel, Olav Lysne, Li-Shiuan Peh, Li Shang, Mithuna Thottethodi,
1 Broadcom Proprietary and Confidential. © 2015 Broadcom Corporation. All rights reserved. MS TIMING CHALLENGES Jacob Rael and Gaurav Mehta.
EE 241 Class Project Substrate Noise Current Injected by Digital IP Cores Stefano Zanella Mentor: Luca Carloni.
WAN Technologies.
Supply Voltage Biasing in Synopsys Andy Whetzel University of Virginia 1.
Impromptu Data Extraction and Analysis Data Mining and Analytics Framework for VLSI Designs Sandeep P
Web-based design Flávio Rech Wagner UFRGS, Porto Alegre, Brazil SBCCI, Manaus, 24/09/00 Informática UFRGS.
Hitendra Divecha Sr. Product Marketing Manager SSV Summit November 21 st, 2013 QRC Extraction.
Introduction to Computer and Programming CS-101 Lecture 6 By : Lecturer : Omer Salih Dawood Department of Computer Science College of Arts and Science.
Overview of SQL Server Alka Arora.
Fast & Furious: Taming the Challenges of Advanced-Node Design Anirudh Devgan, Senior Vice President, Digital & Signoff Group.
Distributed Computation in MANets Robot swarm developed by James Rice University.
Software-defined Networking Capabilities, Needs in GENI for VMLab ( Prasad Calyam; Sudharsan Rajagopalan;
11 Workshop on Information Technology March Shanghaï CONFIDENTIAL Architectures & Digital IC design.
Research in IC Packaging Electrical and Physical Perspectives
Department of Communication Engineering, NCTU
Taking the Complexity out of Cluster Computing Vendor Update HPC User Forum Arend Dittmer Director Product Management HPC April,
High Performance Embedded Computing © 2007 Elsevier Lecture 3: Design Methodologies Embedded Computing Systems Mikko Lipasti, adapted from M. Schulte Based.
Cellular Phones as Embedded Systems by Niam Amarnani.
High Performance Embedded Computing © 2007 Elsevier Chapter 1, part 2: Embedded Computing High Performance Embedded Computing Wayne Wolf.
Chonnam national university VLSI Lab 8.4 Block Integration for Hard Macros The process of integrating the subblocks into the macro.
1. Process Gather Input – Today Form Coherent Consensus – Next two months.
University of Catania Computer Engineering Department 1 Educational tools for complex topics: a case study for Network Based Control Systems Prof. Orazio.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
Parallel and Distributed Simulation Introduction and Motivation.
PRESENTED BY, SARANYA , GAYATHRI, II ECE-B.
Agenda Motion Imagery Challenges Overview of our Cloud Activities -Big Data -Large Data Implementation Lessons Learned Summary.
Pascucci-1 Valerio Pascucci Director, CEDMAV Professor, SCI Institute & School of Computing Laboratory Fellow, PNNL Massive Data Management, Analysis,
SSV Summit November 2013 Cadence Tempus™ Timing Signoff Solution.
An accurate and efficient SSO/SSN simulation methodology for 45 nm LPDDR I/O interface Dr. Souvik Mukherjee, Dr. Rajen Murugan (Texas Instruments Inc.)
November 2013 Review Talks Morning Plenary Talk – CLAS12 Software Overview and Progress ( ) Current Status with Emphasis on Past Year’s Progress:
Testability of Analogue Macrocells Embedded in System-on-Chip Workshop on the Testing of High Resolution Mixed Signal Interfaces Held in conjunction with.
Optimization for Leakage Power Reduction using Multi-Threshold Voltages for High Performance Microprocessors Jeegar Shah, Marius Evers, Jeff Trull, Alper.
Mehdi Ghayoumi MSB rm 132 Ofc hr: Thur, a Machine Learning.
Workshop - November Toulouse Astrium Use Case.
Tool Benchmarking Where are we? Justin E. Harlow III Semiconductor Research Corporation April 9, 2001.
REALITY STATISTICAL CHARACTERIZATION OF A HIGH-K METAL GATE 32NM ARM926 CORE UNDER PROCESS VARIABILITY IMPACT Paul Zuber Petr Dobrovolny Miguel Miranda.
1 Grid Activity Summary » Grid Testbed » CFD Application » Virtualization » Information Grid » Grid CA.
ASIC Building Blocks for Tracker Upgrade A. Marchioro / CERN-PH-ESE October, 2009.
© 2012 Cisco and/or its affiliates. All rights reserved. Cisco Confidential 1.
Static Timing Analysis
An Architectural Approach to Managing Data in Transit Micah Beck Director & Associate Professor Logistical Computing and Internetworking Lab Computer Science.
Tackling I/O Issues 1 David Race 16 March 2010.
High Risk 1. Ensure productive use of GRID computing through participation of biologists to shape the development of the GRID. 2. Develop user-friendly.
MUX-2010 DISCUSSION : W HAT DO WE NEED NEXT IN HEP.
RD53 1.  Full/large demonstrator chip submission ◦ When: 2016 A.Early 2016: If chip must have been fully demonstrated in test beams for TDRs to be made.
Research in Computer Graphics, Visualization and Human- Computer Interaction CSc 8900/9900 Ying Zhu Associate Professor Department of Computer Science.
Design and Planning Tools John Grosh Lawrence Livermore National Laboratory April 2016.
Mixed Signal STA Ben Farhat – Cadence Design Systems Tau conference – March/2015.
Overview of MSU ESRDC Activities related to Computational Tools for Early State Design Dr. Noel Schulz Associate Professor and TVA Endowed Professorship.
Thermal Aware EM Computation
Mixed-Digital/Analog Simulation and Modeling Research
Analytics and OR DP- summary.
Top-level Schematics Digital Block Sign-off Digital Model of Chip
POWSYBL “Power System Blocks”
HUMAN AND SYSTEMS ENGINEERING:
Measuring the Gap between FPGAs and ASICs
Panel on Research Challenges in Big Data
Presentation transcript:

© 2014 Synopsys. All rights reserved.1 Wheres my glass slipper? TAU 2014 Nanda Gopal Director R&D, Characterization

© 2014 Synopsys. All rights The Center of the Design Universe Characterization Characterization Simulation TCAD Circuit Design IT modeling optimization correlation resource overload convergence correlation Extraction correlation

© 2014 Synopsys. All rights reserved.3 Challenges FINFETs Parasitics Circuit design Technology Complex cells Macros Memories Cell Complexity Noise Statistical IO Model Complexity Low power Leakage Power #Cells #Corners Resources Scalability Performance Validation Tools/flows IP issues Qualification

© 2014 Synopsys. All rights reserved.4 The Characterization Engineer Circuit Theory Algorithms Databases Distributed Computing Programming Interface Design Circuit Simulation Digital Design Static Timing Analysis Power Analysis

© 2014 Synopsys. All rights reserved.5 Collaboration is a Must

© 2014 Synopsys. All rights reserved.6 Characterization is your Cinderalla! Characterization is critical at advanced nodes today: –It is at the confluence of analog and digital –It provides the base for implementation –It enables new technologies and models –It is the glue across tools and flows –It has to be the first thought of tool developers and users alike Neglect characterization at your own peril!

© 2014 Synopsys. All rights reserved.7 Thank You