COMPUTER ORGANIZATION AND ARCHITECTURE 15EM2001 COMPUTER ORGANIZATION AND ARCHITECTURE © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Input / Output The computer system's input/output (I/O) architecture is its interface to the outside world. The two important modules of the computer system - The processor and The memory module. The third key component of a computer system is a set of I/O modules Each I/O module interfaces to the system bus and controls one or more peripheral devices. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Why an I/O device or peripheral device is not directly connected to the system bus? 1. There are a wide variety of peripherals with various methods of operation. 2. The data transfer rate of peripherals is often much slower than that of the memory or processor. 3. Peripherals often use different data formats and word lengths than the computer to which they are attached © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Input/output Modules The major functions of an I/O module are categorized as follows – Control and timing Processor Communication Device Communication Data Buffering Error Detection © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Processor & Device Communication Control & timings The I/O function includes a control and timing requirement to co-ordinate the flow of traffic between internal resources and external devices. During the I/O operation, the I/O module must communicate with the processor and with the external device Processor & Device Communication © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Processor communication involves the following – Command decoding Data Status Reporting Address Recognition © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Data Buffering Error Detection An essential task of an I/O module is data buffering The data buffering is required due to the mismatch of the speed of CPU, memory and other peripheral devices. Error Detection Another task of I/O module is error detection and for subsequently reporting error to the processor. One class or error includes mechanical and electrical malfunctions reported by the device (e.g. paper jam). © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Block diagram of I/O Module Interface to System Bus Interface to External Devices Data Register External Devices Interface Logic Data Status Data Lines Command Status/Control Register I/O Logic External Devices Interface Logic Data Address Lines Status Control Lines Command © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

I/O Controller Control/Status Registers Data registers CPU tells device what to do --- write to control register CPU checks whether task is done --- read status register Data registers CPU transfers data to/from device Device electronics Performs actual operation © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Input from Keyboard When a character is typed: Its ASCII code is placed in bits [7:0] of KBDR The ready bit KBSR[15] is set to 1 Keyboard is disabled, any typed characters will be ignored When KBDR is read: KBSR[15] is set to 0 Keyboard is enabled © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Basic Input Routine © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Output to Monitor When monitor is ready to display another character: The ready bit DSR[15] is set to 1 When data is written to DDR: DSR[15] is set to 0 Character in DDR[7:0] is displayed Any other character data written to DDR is ignored © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Basic Output Routine © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Two types of addressing are possible – Memory-mapped I/O Isolated or I/O mapped I/O © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Memory-mapped I/O There is a single address space for memory locations and I/O devices The processor treats the status and address register of the I/O modules as memory location and the same machine instructions are used to access both memory and I/O devices. For example, if the size of address bus of a processor is 16, then there are 216 combinations and all together 216 address locations can be addressed with these 16 address lines. Since I/O devices are included in the same memory address space, so the status and address registers of I/O modules are treated as memory location by the processor. Therefore, the same machine instructions are used to access both memory and I/O devices. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Isolated or I/O -mapped I/O In this scheme, the full range of addresses may be available for both. The address refers to a memory location or an I/O device is specified with the help of a command line. In general command line is used to identify a memory location or an I/O device. if =1, it indicates that the address present in address bus is the address of an I/O device. if =0, it indicates that the address present in address bus is the address of a memory location. Since full range of address is available for both memory and I/O devices, so, with 16 address lines, the system may now support both 216 memory locations and 216 I/O addresses. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Data Transfer Require control signals Synchronous : All devices derive the timing information from common clock line. Asynchronous: No common clock Require control signals Strobe Pulse Handshaking © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Strobe Control © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Handshaking Source initiated transfer using handshake Block Diagram Timing Diagram Sequence of events © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Handshaking Destination initiated transfer using handshake Block Diagram Timing Diagram Sequence of events © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Input / Output Subsystem There are three basic forms of input and output systems – Programmed I/O Interrupt driven I/O Direct Memory Access(DMA) © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Programmed I/O: With programmed I/O, the processor executes a program that gives its direct control of the I/O operation, including sensing device status, sending a read or write command, and transferring the data. Interrupt driven I/O: With interrupt driven I/O, the processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the I/O module completes its work. DMA: In Direct Memory Access (DMA), the I/O module and main memory exchange data directly without processor involvement. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

I/O Commands There are four types of I/O commands that an I/O module will receive when it is addressed by a processor – Control Test Read Write © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Programmed I/O With programmed I/O, the processor executes a program that gives its direct control of the I/O operation, including sensing device status, sending a read or write command, and transferring the data. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Example Data transfer from I/O device to CPU Flow chart for CPU program to input data © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Interrupt driven I/O With interrupt driven I/O, the processor issues an I/O command, continues to execute other instructions, and is interrupted by the I/O module when the I/O module completes its work. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Daisy chain priority interrupt © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Parallel priority interrupt Truth Table of priority encoder from CPU © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Direct Memory Access (DMA) © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

DMA Transfer © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Direct Memory Access © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

DMA I/O Operation © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

DMA Modes of Operation Single Transfer at a time and then release of the hold on the system bus. Burst Transfer at a time and then release of the hold on the system bus. A burst may be of a few kB. Bulk Transfer and then release of the hold on the system bus after the transfer is completed. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Input/Output Processor- Channel Block diagram of a computer with l/O processor © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Channel / CPU Communication © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Computer System using Different Interface Standards ISA---Industry Standard Architecture, SCS-Small Computer System, IDE---Integrated Drive Electronics © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

PCI PCI is developed as a low cost bus that is truly processor independent. It supports high speed disk, graphics and video devices. PCI has plug and play capability for connecting I/O devices. To connect new devices, the user simply connects the device interface board to the bus. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

PCI Bus in a Computer System © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

SCSI Bus (Small Computer System Interface) SCSI refers to the standard bus which is defined by ANSI (American National Standard Institute). SCSI bus the several options. It may be, Narrow bus: It has 8 data lines & transfers 1 byte at a time. Wide bus: It has 16 data lines & transfer 2 byte at a time. Single-Ended Transmission: Each signal uses separate wire. HVD (High Voltage Differential): It was 5v (TTL cells) LVD (Low Voltage Differential): It uses 3.3v © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

USB – Universal Serial Bus USB supports 3 speed of operation. They are,  Low speed (1.5Mb/s)  Full speed (12mb/s)  High speed ( 480mb/s) The USB has been designed to meet the key objectives. They are,  It provide a simple, low cost & easy to use interconnection s/m that overcomes the difficulties due to the limited number of I/O ports available on a computer.  It accommodate a wide range of data transfer characteristics for I/O devices including telephone & Internet connections.  Enhance user convenience through ‘Plug & Play’ mode of operation. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Video Display Devices The most commonly used output device is a graphics video monitor. The operations of most video monitors are based on the standard cathode-ray-tube (CRT) design. How the Interactive Graphics display works The modern graphics display is extremely simple in construction. It consists of three components: 1- A digital memory, or frame buffer, in which the displayed Image is stored as a matrix of intensity values. 2- A monitor 3- A display controller, which is a simple interface that passes the contents of the frame buffer to the monitor. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 42

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Cathode-Ray-Tubes © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Raster Scan Electron beam swept across screen one row at a time from top to bottom Each row is referred to as a scan line A raster scan system displays an object as a set of discrete points across each scan line © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Picture elements: screen point referred as “Pixel” Raster-Scan Displays Picture elements: screen point referred as “Pixel” Picture information stored in refresh (frame) buffer © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Raster Scan © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Random-Scan or Vector Scan Display Principles Calligraphic Displays also called vector, stroke or line drawing graphics Electron beam directed only to the points of picture to be displayed. Vector displays, electron beams trace out lines to generate pictures Picture stores as a set of line-drawing commands Storage referred as display list, refresh display file, vector file or display program © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Sample of Random-Scan displays principles © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Images are described in terms of line segments rather than pixels Display processor cycles through the commands © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Vector Scan Display © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Advantages to Raster Displays lower cost filled regions/shaded images Disadvantages to Raster Displays a discrete representation, continuous primitives must be scan-converted (i.e. fill in the appropriate scan lines) Aliasing or "jaggies" Arises due to sampling error when converting from a continuous to a discrete representation © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

geometry objects (lines) whereas raster only handles pixels Advantages of vector: very fine detail of line drawings (sometimes curves), whereas raster suffers from jagged edge problem due to pixels (aliasing, quantization errors) geometry objects (lines) whereas raster only handles pixels eg. 1000 line plot: vector display computes 2000 endpoints raster display computes all pixels on each line © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Secondary Storage The devices need to store information permanently are either magnetic or optical devices. Magnetic Devices: Optical Devices: Magnetic disk ( Hard disk ) CD- ROM Flopy disk CD-Recordable( CD –R) Magnetic tape CD-R/W DVD © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Figure: Fixed and Movable head disk © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Figure: Multiple platter disk © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

The organization of data on a disk is shown in the figure below. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Disk Performance Parameters Seek Time Rotational Delay Transfer Time © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Seek Time Seek time is the time required to move the disk arm to the required track. The seek time is approximated as where Ts = estimated seek time n = number of tracks traversed m = constant that depends on the disk drive s = startup time © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Rotational Delay Disk drive generally rotates at 3600 rpm, i.e., to make one revolution it takes around 16.7 ms. Thus on the average, the rotational delay will be 8.3 ms. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Transfer Time The transfer time to or from the disk depends on the rotational speed of the disk and it is estimated as where T = Transfer time b = Number of bytes to be transferred N = Numbers of bytes on a track r = Rotational speed, in revolution per second The total average access time can be expressed as where Ts is the average seek time. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED