Introduction to 5685x Series TMS320C5510 Addressing Modes Absolute Reference a location by supplying all or part of address as a constant in an instruction Direct Reference a location using a register and an address offset Indirect Reference a location using a pointer Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Absolute Addressing k16 absolute k23 absolute I/O absolute Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Absolute Addressing: k16 absolute Uses the operand *abs16(#k16), where k16 is a 16-bit unsigned constant DPH (7-bit high part of XDP register) and k16 concatenated to form the 23-bit data-space address Example: MOV *abs16(#2002h), T2 Address generated for DPH = 4 is: DPH:k16 = 04 2002h Note: the k16 constant is encoded in a 2-byte extension to the instruction. Instruction using absolute addressing cannot be executed in parallel. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Absolute Addressing: k23 absolute Uses the operand *(#k23), where k23 is a 23-bit unsigned constant specifying the 23-bit data-space address. Example: MOV *(#042002h), T2 Address generated is: k23 = 04 2002h Note: the k23 constant is encoded in a 3-byte extension to the instruction (MSB of 3-byte extension is discarded). Instruction using absolute addressing cannot be executed in parallel. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Absolute Addressing: I/O absolute Uses the operand port(#k16), where k16 is a 16-bit unsigned constant specifying the 16-bit I/O-space address. Example: MOV port(#2002h), T2 I/O address generated is: k16 = 2002h Note: the k16 constant is encoded in a 2-byte extension to the instruction. Instruction using absolute addressing cannot be executed in parallel. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing DP direct SP direct Register bit-direct PDP direct Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing: DP direct @ symbol used before specified address Uses the XDP (extended Data Page DPH:DP) register in addition to an offset to form the 23-bit address = DPH: (DP + Doffset) The most significant 7 bits of address are specified by the 7-bit DPH register to select one of the 128 data pages (0 to 127) The 16 least significant bits are sum of 2 values: 16-bit value in the DP (data page) register + 7-bit offset (Doffset) calculated by assembler. Calculation of 7-bit offset Doffset is different for a data memory and a memory mapped register. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing: DP direct Computation of Doffset for a data memory: Doffset = (Daddr - .dp) & 7Fh where Daddr is the specified 16-bit address in instruction .dp is a 16-bit value assigned with the .dp assembler directive (.dp is generally set to match DP). Example: AMOV #042002h, XDP .dp #2002h MOV @02003h, T2 Doffset = (2003h – 2002h) & 7Fh = 01h 23-bit address = DPH:(DP + Doffset) = 04:(2002h + 0001h) = 04 2003h Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing: DP direct Computation of Doffset for a memory mapped register: Doffset = Daddr & 7Fh where Daddr is the specified 16-bit address in instruction; .dp is not used The mmap() instruction qualifier forces the CPU to behave as if XDP = DPH: DP = 00 0000 Example for XDP = 03 FFF0h: MOV mmap(@AR0), T2 Doffset = Daddr & 7Fh = 0010h & 7Fh = 10h 23-bit address = DPH:(DP + Doffset) = 00:(0000h + 0010h) = 00 0010h Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing: DP direct Note: The addresses 00 0000h to 00 005Fh on the first data page are reserved for memory mapped register. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing: SP direct The XSP register in addition to a 7-bit offset is used to form the 23-bit address. 23-bit address = SPH: (SP + offset) where SPH gives the most significant 7 bits and (SP + offset) give the least significant 16 bits. Uses the operand *SP(offset), where offset is a 7-bit constant. Example for XSP = SPH:SP = 00 FF00h MOV *SP(2), T2 23-bit address = SPH:(SP + offset) = 00:(FF00h + 0002h) = 00 FF02h Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing: Register-bit direct Used to access one register bit or two adjacent register bits in the accumulators (AC0 to AC3), auxiliary registers (AR0 to AR7), and temporary registers (T0 to T3). Uses an offset @bitoffset to specify a bit address as an offset from the LSB of the considered register. Example: BSET @1, AC0 The CPU sets bit 1 of AC0 Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Direct Addressing: PDP direct Used to access a location in I/O space using the port(@Poffset) operand in the instruction. Uses the 9-bit PDP (Peripheral Data Page) register and the 7-bit offset (Poffset) to specify the 16-bit I/O address: 16-bit I/O address = PDP: Poffset The 9-bit PDP register selects one of 512 peripheral data pages (0 to 511); each page is 128 words (0 to 127). Within a selected page, the 7-bit offset selects a word. Example for PDP = 004h: MOV port(@02h), T2 16-bit I/O address: 0202h = 0000 0010 0000 0010 Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing AR indirect Dual AR indirect CPD indirect Coefficient indirect Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: AR indirect Uses one of the auxiliary registers (AR0-AR7) to point to data. Address generation depends on whether one is accessing data space (memory or mmr), register bits, or I/O space. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: AR indirect Accessing Data Space (memory or registers): 23-bit address = ARnH: ARn where ARnH is the high part of XARn = ARnH: ARn and supplies the 7 most significant bits, and ARn supplies the 16 least significant bits Example: MOV *AR0, T2 23-bit address = AR0H: AR0 = XAR0 The CPU reads the value at address XAR0 and loads it into T2. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: AR indirect Accessing a register bit: The selected 16-bit ARn register contains a bit number Example for AR2 = 30: BSET *AR2, AC2 The CPU sets bit 30 of AC2. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: AR indirect Accessing I/O space: The selected 16-bit ARn register contains the complete 16-bit I/O address. Example for AR2 = 0080h: MOV port(*AR2), T2 The CPU reads the value at I/O address 0080h and loads it in T2. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: Dual AR indirect Used to make two data-memory accesses through AR0-AR7. As in AR indirect, extended registers XARn used to generate each 23-bit address. Example 1: Two data-memory accesses ADD *AR0, *AR1, AC0 Example 2: Two instructions in parallel MOV *AR1, T2 || AND *AR2, T1, AC0 Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: CDP indirect Uses the CDP (Coefficient Data Pointer) to point to data. The generation of 23-bit address depends on the access type: data space, register bit, or I/O space. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: CDP indirect Data Space Access (memory or registers): 23-bit address = CDPH: CDP where CDPH is the high part of the extended coefficient data pointer (XCDP = CDPH:CDP) and supplies the 7 MSB of 23-bit address, and CDP supplied the 16 LSB of 23-bit address. Example 1: MOV *CDP, T1 23-bit address = CDPH:CDP = XCDP Example 2: MOV *CDP+, T2 Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: CDP indirect Register Bits: CDP is used to access a register bit CDP contains the bit number Example: BSET *CDP, AC0 Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: CDP indirect I/O Space: The CDP contains the complete 16-bit I/O address. Example: MOV port(*CDP), T2 Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: Coefficient indirect Same address generation as CDP indirect. This mode is mainly used with instructions performing operations on three memory operands per cycle. Two of the operands are accessed using the dual AR indirect addressing mode Third operand is accessed using the coefficient indirect mode Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: Coefficient indirect Example: MPY *AR1, *CDP, AC0 :: MPY *AR2, *CDP, AC1 The values pointed to by AR1, AR2 and CDP are accessed in one cycle. Introduction to 5685x Series Thursday, May 09, 2019

Introduction to 5685x Series TMS320C5510 Addressing Modes Indirect Addressing: pointer operations Both pointer modification and address generation are linear or circular according to the pointer (register) configuration in status register ST2_55. All additions to and subtractions from the pointers are done modulo 64K. One cannot address data across main data pages without changing the value of ARnH of XARn. Introduction to 5685x Series Thursday, May 09, 2019