November 2005 doc.: IEEE 802.11-05/1051r0 09/05/2019 Simulation result for Preliminary PHY proposal and alternative proposed set of Guard Chip Date: 2013-2-04 Authors: Notice: This document has been prepared to assist IEEE DYSPAN SC. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor grants a free, irrevocable license to the IEEE to incorporate material contained in this contribution, and any modifications thereof, in the creation of an IEEE Standards publication; to copyright in the IEEE’s name any IEEE Standards publication even though it may include portions of this contribution; and at the IEEE’s sole discretion to permit others to reproduce in whole or in part the resulting IEEE Standards publication. The contributor also acknowledges and accepts that this contribution may be made public by IEEE DYSPAN SC. Patent Policy and Procedures: The contributor is familiar with the IEEE Patent Policy and Procedures <http:// ieee802.org/guides/bylaws/sb-bylaws.pdf>, including the statement "IEEE standards may include the known use of patent(s), including patent applications, provided the IEEE receives assurance from the patent holder or applicant with respect to patents essential for compliance with both mandatory and optional portions of the standard." Early disclosure to the Working Group of patent information that might be relevant to the standard is essential to reduce the possibility for delays in the development process and increase the likelihood that the draft publication will be approved for publication. Please notify the Chair <harada@nict.go.jp> as early as possible, in written or electronic form, if patented technology (or technology under patent application) might be incorporated into a draft standard being developed within IEEE DYSPAN SC. If you have questions, contact the IEEE Patent Committee Administrator at <patcom@ieee.org>. Slide 1 Mujtaba (Agere), Petranovich (Conexant), Fischer (Broadcom), Stephens (Intel) et. al.

09/05/2019 09/05/2019 Abstract This contribution presents the revised simulation results supported for the Preliminary PHY Proposal for IEEE 1900.7 System (doc.:1900.7-13-0054-00-CNTR ) Also it presents a revised method to determine the optimum values of guard chip for multi-code DSSS based PHY design. Slide 2

PHY Design (1/2) Items Spec 1 Spec 2 Modulation Scheme QPSK 09/05/2019 PHY Design (1/2) Items Spec 1 Spec 2 Modulation Scheme QPSK Symbol Rate 50ksps 25 ksps Data Rate 100 kbps 50 kbps Number of Sequence 31 63 Sequence 5- stage M-Sequence 6 Stage M-Sequence Guard chip 5 9 Length of extended sequence 36 72 Chip rate 1.8 MHz Cyclic shift interval Number of cyclic shifted code 6 7 Number of pilot channel 1 Number of data channel Max transmission rate 500 kbps 300 kbps

PHY Design (2/2) Items Spec 3 Spec 4 Modulation Scheme QPSK 09/05/2019 PHY Design (2/2) Items Spec 3 Spec 4 Modulation Scheme QPSK Symbol Rate 50ksps 25 ksps Data Rate 100 kbps 50 kbps Number of Sequence 31 63 Sequence 5- stage M-Sequence 6 Stage M-Sequence Guard chip 5 9 Length of extended sequence 36 72 Chip rate 1.8 MHz Cyclic shift interval 1 Number of cyclic shifted code Number of pilot channel Number of data channneel 30 62 Max transmission rate 3 Mbps 3.1 Mbps

Outdoor Channel Model Measure frequency 200MHz Hb=45m Hm=2m BS Power 20W Table 1 shows the calculated RMS Delay Spread based on VHF band measurement results for Japan Public broadband network [1].The average RMS delay spread highly depends on the environment such as terrain type. Index of Measured Points P16 P5 P4 P1 P3 P6 P15 P2 P7 P14 P8 P13 P12 P11 P10 P9 Distance (km) 1.4 1.5 1.6 1.8 2.7 2.8 3.2 4.7 6.1 7.7 9.6 12.3 13.6 15.6 16 RMS Delay Spread (µs) 0.61 029 0.45 0.4 0.82 0.29 7.9 0.74 1.79 20.6 12.2 10.9 8.4 6.5 17.8 [1] M. OODO, N. SOMA, R. FUNADA and H. HARADA, “Channel Model for Broadband Wireless Communication in the VHF-band”, IEICE Technical Report

Indoor channel Model [2] 09/05/2019 [2] Theodore S. Rappaport, Wireless Communications: Principles and Practice (2nd Edition), Prentice Hall, ISBN: 0130422320 Publish Date: Dec 31, 2007

Delay Spread used in the simulation 09/05/2019 Delay Spread used in the simulation Indoor delay spread < 270 ns (2.7e-7) Outdoor delay spread < 0.5 us (5 e-7)

Speed of airplane: 885 km/hr 09/05/2019 54 MHz 806 MHz Fd=400 Hz 7992 km/hr 536 km/hr Fd=100 Hz 1998 km/hr 134 km/hr Fd=40 Hz 799.2 km/hr 53.6 km/hr Speed of airplane: 885 km/hr Speed of bullet train: 300 km/hr Performance for 2 path Rayleigh Fading

Determination of optimum guard CHIP 09/05/2019 Determination of optimum guard CHIP

Guard chips calculation (Spec 3) 09/05/2019 Guard chips calculation (Spec 3) Modulation QPSK 16 QAM 64 QAM Unit Chip Rate 1.8 Mcps Guard Chip x chips Length of chips per symbol 31 + x 31+x Cyclic shift interval 1 Symbol Rate 1.8/(31+x) Msps Max transmission data rate 1.8 *30*2/(31+x) 1.8*30*4/(31+x) 1.8*30*8/(31+x) Mbps Expected data rate for M2M 10 X 5 11 17 Transmission data rate 3 2.6 2.3 6 5.1 4.6 12 10.2 9.2

Data throughput vs. different number of guard chips (Spec 3) 09/05/2019 Data throughput vs. different number of guard chips (Spec 3) These table and chart are based on QPSK modulation scheme. From simulations and calculations, larger number of guard chips obtained fewer number of error shown in the table. However, due to the larger overhead incurred, the effective data throughput is reduced as the the number of guard chip increases as shown on the left. Guard chip (bits) 5 11 17 SNR=20, error (mbps) 0.0336 0.03328 0.03285 SNR=25, error (mbps) 0.0114 0.01066 0.0108 SNR=30, error (mbps) 0.0033 0.00315 0.00312

09/05/2019 Summary From the above simulations and calculations, we find that larger number of guard chip though obtain few number of the error, the effective data throughput is reduced as more overhead bits are involved. Hence, I would like to revised that guard chip 5 and guard chip 9 are better for spec 3 and 4.

09/05/2019 Conclusion In this presentation, a revised simulation results are presented, as well as a revised method of determining the optimum number of guard chip. From the calculations and simulations, we would like to propose to have 5 guardchips for spec 3 and 9 guardchips for spec 4.

Guard chips calculation (Spec 4) 09/05/2019 Appendix Guard chips calculation (Spec 4) Modulation QPSK 16 QAM 64 QAM Unit Chip Rate 1.8 Mcps Guard Chip x chips Length of chips per symbol 63 + x 63+x Cyclic shift interval 1 Symbol Rate 1.8/(63+x) Msps Max transmission data rate 1.8 *62*2/(63+x) 1.8*62*4/(63+x) 1.8*62*8/(63+x) Mbps Expected data rate for M2M 10 X 9 21 33 Transmission data rate 3.1 2.65 2.325 6.2 5.3 4.65 12.4 10.6 9.3