Day 16: October 17, 2011 Performance: Gates ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 16: October 17, 2011 Performance: Gates Penn ESE370 Fall2011 -- DeHon

First Order Delay t = R0C0 R0 = Resistance of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Rdrive = R0/Wn Cg = WC0 Technology independent relative delay t = R0C0 Penn ESE370 Fall2011 -- DeHon

Today Delay in Gates Data Dependent Delay Large Fanin Capacitance in Gates Asymmetry of Inputs Penn ESE370 Fall2011 -- DeHon

Gates Penn ESE370 Fall2011 -- DeHon

Data Dependent Delay Resistance depends on input values delay depends on input data t-delays assuming minsize? Penn ESE370 Fall2011 -- DeHon

How Size How size to equalize worst-case rise/fall times for Rdrive=R0/2? Penn ESE370 Fall2011 -- DeHon

How Size How size for equal rise/fall for Rdrive=R0/2? Penn ESE370 Fall2011 -- DeHon

Input Load Input capacitance in each case? Penn ESE370 Fall2011 -- DeHon

Observe Ratio of Input Load Capacitance to Output Drive Strength: CILoad/Ids Differs with gate function Some gates give more drive per capacitive load we pay Penn ESE370 Fall2011 -- DeHon

How Size Size equalize rise/fall times Rdrive=R0/2? Penn ESE370 Fall2011 -- DeHon

Increasing Fanin What happens to input capacitance as fanin (k) increases Keeping output drive the same E.g. Rdrive=R0/2 k-input nand gate has what input capacitance? Penn ESE370 Fall2011 -- DeHon

Fanin Conclude: gates slow down with fanin Less drive per input capacitance Penn ESE370 Fall2011 -- DeHon

Which is Fastest? nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 Penn ESE370 Fall2011 -- DeHon

Capacitance Voltage each case? Switching DQ? Effective Capacitance? Penn ESE370 Fall2011 -- DeHon

Input (A)Symmetry If one input is known to be later than other, does it matter where it goes? Penn ESE370 Fall2011 -- DeHon

Delay of each implementation? Penn ESE370 Fall2011 -- DeHon

Take Away? Penn ESE370 Fall2011 -- DeHon

Lesson Large gates are slow / inefficient High capacitive load / drive strength Small gates can be inefficient Need many stages Staging over moderate size gates minimizes delay Exact size will be technology dependent Penn ESE370 Fall2011 -- DeHon

Admin Midterm solutions up HW5 Should be able to compute delays, size gates Energy next time Penn ESE370 Fall2011 -- DeHon

Ideas First order reason in t=R0C0 units Gates have different efficiencies Drive strength per unit input capacitance With velocity saturation (short term), nands and nors are similar efficiency Large fanin and fanout slow gates Decompose into stages …but not too much Penn ESE370 Fall2011 -- DeHon