Analysis of history effect in PD-SOI logic Gates FTFC, May 2003 Vincent Liot, Philippe Flatresse

Analysis of History effect in PD-SOI logic gates OUTLINE Introduction PD-SOI MOSFET electrical behaviour History effect Logic gates characterization Accelerated History Effect method for non-monotonous Tp variations Inverter characterization, comparison with inverter chain Complex gates Conclusions May-19 Analysis of History effect in PD-SOI logic gates

PD-SOI device - electrical properties, Floating body effect 5/3/2019 Fast process : capacitive coupling Slow process : Impact ionization, GIDL, Gate current, diodes currents Dynamic Vt in PD-SOI MOSFET : Vt decreases with body charge May-19 Analysis of History effect in PD-SOI logic gates

Logic gates - inverter static state 1053mv at DC1 1180mv at DC0 64mv at DC1 416mv at DC0 Body potential values depend on initial conditions DC0 body potential  DC1 body potential  different Propagation delays May-19 Analysis of History effect in PD-SOI logic gates

Logic gates Steady State, inverter case Body potential (V) Inverter PMOS Steady State after DC1 condition = Steady State after DC0 condition After 100000 to 1 million pulses : logic gate Steady State : needs specific algorithms DC0 body potential  DC1 body potential  SS body potential  3 different propagation delays 1V VB after DC1 VB at Steady State VB after DC0 Inverter NMOS Inverter propagation delays Wn=1um, Wp=3,2um, F=10MHz May-19 Analysis of History effect in PD-SOI logic gates

Logic gates – propagation delay variations Delay variation can be higher than 10% Best and worst cases gate delays can be : At first transisitons after DC equilibrium At Steady State Between first transistions and steady state : non monotonous propagation delay variations Conclusion : PD-SOI standard cells characterization needs a specific methodology to find best and worst cases May-19 Analysis of History effect in PD-SOI logic gates

Accelerated History Effect - Principle Inverter PMOS Quasi linear evolution Fast body potential variation : capacitive couplings Slow body potential deviation across one period VB = 1,5E-4 V Inverter NMOS Body potential evoluates across one period with slow process The slow variation of body potential across one period is linear on a limited number of pulses Principle of the method : measure slow body potential variation across one period and amplificate the slow variation May-19 Analysis of History effect in PD-SOI logic gates

Accelerated History Effect – AHE NMOS subciruit 3 parts : Measurement, charge injection and convergence control May-19 Analysis of History effect in PD-SOI logic gates

AHE – Measurement of slow body variation Voltage (V) 3E-5 VB Clock 2 voltage controlled voltage sources with delays allow the operation : VB=VB(t)-VB(t-période) VB(t) : BI node, VB(t-période) : Bold node May-19 Analysis of History effect in PD-SOI logic gates

Analysis of History effect in PD-SOI logic gates AHE – Charge injection Voltage (V) VB(t) Charge injection Bobj Acc*VB Bold = VB(t-period) 1 voltage controlled voltage source allows the operation Bobj = Bold+ Acc*VB Voltage controlled current source manage charge injection while VB(t)Bobj during clock signal May-19 Analysis of History effect in PD-SOI logic gates

Accelerated history effect – Body potential accelerated evolution NMOS Body potential (V) NMOS Body potential (V) Number of simulated pulses Equivalent number of pulses NMOS body potential evolution : 100 periods with Acc=225, 25 periods with Acc=900 Body potential evolution with real time scale for different accelerations (112 to 900) shows accurate reproduction of circuit history May-19 Analysis of History effect in PD-SOI logic gates

Equivalent number of pulses Number of simulated pulses Accelerated history effect – Inverter delay variation with different accelerations Tp (ps) Tp (ps) Equivalent number of pulses Number of simulated pulses AHE allows to simulate more than 100000 periods with a few tens of pulses May-19 Analysis of History effect in PD-SOI logic gates

AHE - validation at steady state Number of cases % difference of Tp beetween AHE steady state algorithm Harmonic Balance (Anacad) Inverter Wn=1um, Wp=3,2um, C=5fF to 200fF, Slope=10ps to 1000ps, VDD=0,8V to 1,4V Less than 1% difference beetween AHE and SS algorithm  Very accurate method May-19 Analysis of History effect in PD-SOI logic gates

Analysis of History effect in PD-SOI logic gates Inverter – History effect behaviour in characterization space Slope*Load Fall history effect % Rise history effect % Cl (fF) Cl (fF) Slope (ps) Slope (ps) Wn=1um, Wp=3,2um, F=10MHz, VDD=1,2V Maximum history effect at 5fF and 1000ps, 5-6% on falling transition, 10% on rising transition May-19 Analysis of History effect in PD-SOI logic gates

Inverter – Non-monotonous variations Tp Fall variation % Tp Fall variation % S=1000ps C=5fF Number of simulated pulses Number of simulated pulses Wn=1um, Wp=3,2um, F=10MHz, VDD=1,2V NMOS evoluates much faster than PMOS Non-monotonous variations quikly reduce when S decrease or C increase May-19 Analysis of History effect in PD-SOI logic gates

Inverter – Potential evolution and propagation delay variations NMOS charge  positive impact on TpFall, negative impact on TpRise PMOS charge  negative impact on TpFall, positive impact on TpRise   PMOS body charge VB PMOS  Décharge du PMOS VB PMOS  NMOS body charge VB NMOS  non-monotonous Fall  Rise  monotonous Fall  Rise  Décharge du NMOS VB NMOS  Fall  Rise  Fall  Rise  Fall transition of an invertig stage causes Rise transition on the next inverting stage Delay opposite variations induce history effect compensation gate per gate May-19 Analysis of History effect in PD-SOI logic gates

Inverter chain – Delay variation Tp (ps) 12,3ps : 5,8% 6,8ps : 3,3% 1,7ps : 0,85% Number of simulated pulses Wn=1um, Wp=3,2um, S=500ps, C=10fF, F=10MHz May-19 Analysis of History effect in PD-SOI logic gates

Inverter Chain – Gate per gate history effect Tp Fall variation % Tp Rise variation % Number of simulated pulses Number of simulated pulses Wn=1um, Wp=3,2um, S=500ps, C=10fF, F=10MHz Negligible non-monotonous delay variations on three inverter chain, history effect decreases with number of gates May-19 Analysis of History effect in PD-SOI logic gates

History effect in standard cells Inverseur : 1 stage NAND2 : 1 stage, 2 stacked NMOS NOR3 : 1 stage 3 stacked PMOS OR3 : 2 stages, 3 stacked PMOS MUX21 : 2 stages, pass gates XOR : 3 stages, pass gates Latch : 3 stages, pass gates Flip-Flop : 4 stages, pass gates 3 inverters chain Slope = 500ps Load = 10fF History effect decreases as gate complexity increases Slope reduction through the gate Increased capacitance May-19 Analysis of History effect in PD-SOI logic gates

Analysis of History effect in PD-SOI logic gates Conclusion AHE method developped to characterize non-monotonous history effect Valid whatever the partially depleted SOI logic gates Technology and Spice simulators independent History effect history effects are reduced for slow input slope and large load capacitances Carefull design reduces history effect : Low power design means fast input slopes Non-monotonous variations can be neglected due to gate to gate compensation effect Complex gates History effect is reduced through in gates including a large number of stages and/or load capacitances May-19 Analysis of History effect in PD-SOI logic gates

AHE - method improvement End of transistor accelerated evolution, signal for next acceleration Problem : NMOS evoluates much faster than PMOS Calculation of Acc and automatisation of acceleration switch allows large gates characterization May-19 Analysis of History effect in PD-SOI logic gates