Processor Specs CSIT 301 (Blum)

Pentium 4 Processor Specs CSIT 301 (Blum)

The above list of processor specifications includes such aspects as CPU Speed, Bus Speed, Manufacturing technology, Stepping, Cache Size, Package Type CSIT 301 (Blum)

Some more recent processor spec’s CSIT 301 (Blum)

Even more recent CSIT 301 (Blum)

Still even more recent CSIT 301 (Blum)

Intel Core i9 CSIT 301 (Blum)

CPU Speed CSIT 301 (Blum)

CPU Speed CSIT 301 (Blum)

CPU Speed The activities of the processor are kept in sync by the clock. The clock goes through a regular/repetitive action. In a binary system, a cycle consists of a 1 and a 0 (a high followed by a low). The clock is usually a quartz oscillator that is external to the microprocessor. So the CPU speed is not something built into the chip, but rather the maximum rate at which the chip can be expected to perform normally. CSIT 301 (Blum)

CPU Speed (Cont.) Sometimes differently rated chips are made from the same manufacturing process, and the CPU speed is determined by some testing after the fact. Some people try to operate the processor faster than the designated rate. This is known as “overclocking.” CSIT 301 (Blum)

CPU Speed (Cont.) The speed is measured in Hertz, which are cycles per second. KiloHertz, kHz, is thousands (103) of cycles per second MegaHertz, MHz, is millions (106) of cycles per second GigaHertz, GHz, is billions (109) of cycles per second What would be next? CSIT 301 (Blum)

CPU Speed (Cont.) The clock speed is also known as the clock’s frequency (the number of cycles per second). A related quantity is called the period which is the time required for one cycle (a.k.a. as a clock tick). A clock’s frequency and period are reciprocals. f = 1/T or T = 1/f, where f is frequency and T is period E.g. a frequency of 60 Hertz (cycles per second) corresponds to a period of 1/60 = 0.0167 seconds per cycle CSIT 301 (Blum)

CPU Speed (Cont.) A frequency of 1 kHz [a thousand cycles per second] corresponds to a period (tick) of 1 millisecond (ms) [a thousandth (10-3) of a second per cycle]. A frequency of 1 MHz [a million cycles per second] corresponds to a period (tick) of 1 microsecond (s) [a millionth (10-6) of a second per cycle]. A frequency of 1 GHz [a billion cycles per second] corresponds to a period (tick) of 1 nanosecond (ns) [a billionth (10-9) of a second per cycle]. CSIT 301 (Blum)

Question If the processor speed is 3.20 GHz, what is the corresponding period? Approach 1: 3.20 GHz  3.20 x 109 Hz T = 1/f  1/3.20 x 109 Hz = 0.0000000003125 s = 0. 0000003125 ms = 0.0003125 μs = 0.3125 ns Approach 2: 1/3.20 GHz = 0.3125 ns (just know reciprocal of GHz is ns) CSIT 301 (Blum)

Intel’s Turbo Boost CSIT 301 (Blum)

Turbo Boost Instead of having a fixed top speed, the microprocessor has built-in sensors for current, power usage, and temperature. Based on these factors and computational need, it will push the speed for one or more cores to its limit. CSIT 301 (Blum)

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Bus Speed CSIT 301 (Blum)

Bus Speed CSIT 301 (Blum)

Bus Speed There is a hierarchy of buses in a computer, but in a discussion of processors, the buses of interest are the front-side bus and the back-side bus. In early processors the CPU speed and bus speed (and thus the speed of interactions with memory, etc.) were the same. But a bottleneck (the von Neumann bottleneck) arose because memory speeds cannot keep up with processor speeds. And so accessing the memory was holding the processor back. CSIT 301 (Blum)

Front-side Bus (FSB) The Front-side Bus (a.k.a. the memory bus or system bus) connects the processor to other parts via the chipset. It allows communication between the processor and main memory (RAM), the system chipset, PCI devices, the AGP card, and other peripheral buses. When the “bus speed” is given as one of the processor’s specs it usually refers to the front-side bus speed. CSIT 301 (Blum)

The Northbridge A chipset is a simply group of chips that work together to perform related functions. The Northbridge chipset communicates with the processor (using the FSB) and controls interaction with memory, the PCI bus, and AGP. Northbridge’s partner in the chipset is the Southbridge. The Southbridge handles the IO functions. The Intel Hub Architecture (IHA) replaced the Northbridge/Southbridge chipset. CSIT 301 (Blum)

No longer separate With Moore’s law, we moved from chipset to chips (more circuitry and therefore more functionality on one integrated circuit). Then the Northbridge and Southbridge stopped were no longer separate chips. However, the disparity in speeds still exists and one might talk of “Northbridge functionality” and “Southbridge functionality.” CSIT 301 (Blum)

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QPI: Quick Path Interconnect CSIT 301 (Blum)

UPI: Ultra Path Interconnect CSIT 301 (Blum)

GT/s CSIT 301 (Blum)

Extra bits We have discussed sending extra bits for Error Detection and/or Error Correction. There are also extra bits one sends for timing purposes – to keep in sync. The switch to the GT/s specification was to report the actual data being transferred; it does not include these timing bits. CSIT 301 (Blum)

Backside Bus The back-side bus (a.ka. the cache bus) connects the processor to L2 cache. The term back-side bus is reserved for cases in which the L2 cache is packaged with the microprocessor. If the L2 cache is separate from the processor (OLD), the front-side bus will connect the processor to the Level 2 cache. Now even L3 is “on die” Cache (SRAM) operates faster than memory (DRAM). The backside bus operates at faster speeds than the front-side bus, sometimes it works at the processor speed. CSIT 301 (Blum)

FSB Speeds The ratio between the CPU speed and bus speed is a simple fraction. For example, a CPU speed of 3.2 GHz and bus speed of 800 MHz has a ratio of 4. With Pentium III’s the 100 and 133 MHz FSB speeds became standard. That rate has been somewhat fixed for a few years but what is changing is the amount of data transferred each clock cycle. This is where one begins to talk of “DDR” or “quad-pumped.” CSIT 301 (Blum)

Edge-triggering CSIT 301 (Blum)

Edge triggering The clock keeps the various circuit elements working in unison. Elements are typically designed to be active on the “edge” of the clock – either when it is rising (the positive edge) Or when it is falling (the negative edge) More precise than level activation, where the action takes places when the clock has a certain state or level (e.g. when the clock is high). CSIT 301 (Blum)

DDR Double Data Rate (DDR) allows data to be fetched on both the positive and negative edges of the clock. Thus it is essentially the equivalent of doubling clock rate. E.g. a 100MHz DDR transfer equals that of a 200MHz SDR transfer CSIT 301 (Blum)

Quad pumped A quad pumped bus allows four signals to be communicated per clock cycle. This is sometimes called QDR (Quad Data Rate). Pentium 4’s used a quad pumped FSB. The 400MHz FSB is a 100MHz bus with four signals per cycle. The 533MHz FSB is a quad-pumped 133MHz bus. Quad pumping was one of the features of the Pentium 4 Net-Burst micro-architecture. CSIT 301 (Blum)

DDR3 CSIT 301 (Blum)

DDR, DDR2, & DDR3 CSIT 301 (Blum)

http://ark.intel.com/products/63696/Intel-Core-i7-3960X-Processor-Extreme-Edition-%2815M-Cache-3_30-GHz%29 CSIT 301 (Blum)

DDR4 CSIT 301 (Blum)

Intel’s QuickPath With multiple cores, now the chip has a built-in memory controller (Integrated Memory Controller) per core and each core gets assigned part of the system memory. CSIT 301 (Blum)

Manufacturing Technology CSIT 301 (Blum)

Manufacturing technology CSIT 301 (Blum)

Manufacturing Technology CSIT 301 (Blum)

Aka “Lithography” CSIT 301 (Blum)

“Tick Tock” Intel refers to their progress as “tick-tock” Tick is an improvement in manufacturing technology – a decrease in the component size (Moore’s Law) Tock is a change in the architecture – new instructions, more controllers, more registers, etc. CSIT 301 (Blum)

Manufacturing technology (lithography) The next specification found in the table is manufacturing technology, which indicates the size of the components (mainly transistors) which reflects the number of components that can be placed on the chip. In earlier microprocessors, one used terms like large-scale integration (LSI), very large-scale integration (VLSI) and ultra large-scale integration (ULSI). But as Moore’s Law continued to hold true, we ran out of adjectives. CSIT 301 (Blum)

Manufacturing Technology Today the manufacturing technology is given in terms of microns or nanometers (e.g. the 0.13-micron or the 90-nm technology). A nanometer (nm) is a billionth of a meter (10-9 m). The same chip may be made using different technologies, but this is to done to perfect the newer technology so that more components can be added to latter chips. CSIT 301 (Blum)

Intel on the 32nm technology CSIT 301 (Blum)

http://www.intel.com/content/www/us/en/silicon-innovations/intel-22nm-technology.html?wapkw=moore%27s+law CSIT 301 (Blum)

Sandy Bridge/Ivy Bridge CSIT 301 (Blum)

14nm to 10nm CSIT 301 (Blum)

Stepping CSIT 301 (Blum)

http://ark.intel.com/products/63696/Intel-Core-i7-3960X-Processor-Extreme-Edition-%2815M-Cache-3_30-GHz%29 CSIT 301 (Blum)

Stepping As with software, mistakes (errata) in hardware are found and revisions are needed. However, hardware mistakes are more difficult to fix. The stepping refers to various fixes, so one wants a higher stepping which presumably has fewer bugs. AMD uses the term “revision number.” The circuitry cannot be changed on an existing chip, it might be possible to overcome a processor bug by changing the BIOS which can be changed (flashed). CSIT 301 (Blum)

Pentium 4 Product Information CSIT 301 (Blum)

Document on Specification Update (Stepping Levels) CSIT 301 (Blum)

Cache size CSIT 301 (Blum)

Cache size CSIT 301 (Blum)

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Cache Recall that there are three levels of cache (L1, L2 and L3) associated with the processor. The cache specification on the previous slide refers to L2 cache. A more detailed set of specification will reveal the amount of L1 and L2 as well as the amount of L3 that can be supported. CSIT 301 (Blum)

Shared or not With multicore a question comes up with L2 cache of whether each core should have its own cache or whether the cache should be shared among the cores. CSIT 301 (Blum)

Cache coherence CSIT 301 (Blum)

L3 The term L3 is starting to be used as for cache on the chip, but in addition to speed and use, another distinction is that each core has its own L2 now whereas L3 is shared. CSIT 301 (Blum)

TDP With more smaller components on today’s chips, there is potentially a lot of heat generation. TDP is thermal design power and is a spec that Intel has started reporting on their processors. It is measured in watts. CSIT 301 (Blum)

References PC Hardware in a Nutshell, Thompson and Thompson http://www.webopedia.com http://www.intel.com http://www.anandtech.com http://www.mbreview.com/lga775.php CSIT 301 (Blum)

References (Cont.) http://www.intel.com/technology/architecture-silicon/next-gen/whitepaper.pdf http://en.wikipedia.org/wiki/SSE4 http://software.intel.com/en-us/articles/software-techniques-for-shared-cache-multi-core-systems/?wapkw=(cache) CSIT 301 (Blum)