Synthesis of multiple rail phase encoding circuits Andrey Mokhov, Crescenzo D’Alessandro, Alex Yakovlev Microelectronics System Design Group, School of EECE, Newcastle University, UK {andrey.mokhov, crescenzo.dalessandro, alex.yakovlev} @ ncl.ac.uk UK Asynchronous Forum, September 2008

Outline Phase encoding Conditional partial order graphs Circuit synthesis Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder Conclusions and future work Outline UK Asynchronous Forum, September 2008

Phase encoding ‘abdc’ symbol Self-synchronous data communication protocol introduced by D'Alessandro et al [ PATMOS’05 ] Reliability to single event upsets High information capacity No scalable implementations of multiple rail controllers ‘abdc’ symbol sensitive interval 4-wire channel: 4! = 24 symbols > 24 = 16 binary symbols log(n!) ≈ n·log(n) Phase encoding UK Asynchronous Forum, September 2008

Comparison with DI communication protocols Phase encoding UK Asynchronous Forum, September 2008

n-wire phase encoding channel UK Asynchronous Forum, September 2008

Outline Phase encoding Conditional partial order graphs Circuit synthesis Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder Conclusions and future work Outline UK Asynchronous Forum, September 2008

Conditional Partial Order Graphs [ DATE’08 ] Conditional Partial Order Graphs UK Asynchronous Forum, September 2008

Controllers synthesis using CPOGs CPOG model can be used for phase encoding controllers specification and synthesis: Vertices correspond to the signal transitions in the channel Conditional arcs determine the order of the transitions 2-wire phase encoder specification example: Conditional Partial Order Graphs UK Asynchronous Forum, September 2008

Outline Phase encoding Conditional partial order graphs Circuit synthesis Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder Conclusions and future work Outline UK Asynchronous Forum, September 2008

Phase detector Decodes phase encoded symbols by detecting the relative order between all the pairs of transitions Consists of n(n-1)/2 mutual exclusion (mutex) elements Circuits synthesis UK Asynchronous Forum, September 2008

Outline Phase encoding Conditional partial order graphs Circuit synthesis Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder Conclusions and future work Outline UK Asynchronous Forum, September 2008

Matrix phase encoder 1 → 2 → 3 1 → 3 → 2 2 → 1 → 3 2 → 3 → 1 3 → 1 → 2 Generates phase encoded symbols given the matrix X = {xkj} of pairwise comparisons of the output transitions 1 → 2 → 3 1 → 3 → 2 2 → 1 → 3 2 → 3 → 1 3 → 1 → 2 3 → 2 → 1 Circuits synthesis UK Asynchronous Forum, September 2008

Matrix phase encoder (implementation) Circuits synthesis UK Asynchronous Forum, September 2008

Matrix phase encoder (implementation) Circuits synthesis UK Asynchronous Forum, September 2008

Outline Phase encoding Conditional partial order graphs Circuit synthesis Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder Conclusions and future work Outline UK Asynchronous Forum, September 2008

One hot phase encoder Generates phase encoded symbols given one hot data X = {x1…xn!} # Control signals Order 1 (1,0,0,0,0,0) a, b, c 2 (0,1,0,0,0,0) a, c, b 3 (0,0,1,0,0,0) b, a, c 4 (0,0,0,1,0,0) b, c, a 5 (0,0,0,0,1,0) c, a, b 6 (0,0,0,0,0,1) c, b, a Circuits synthesis UK Asynchronous Forum, September 2008

One hot phase encoder (logic optimisation) The synthesised CPOG can be optimised Circuits synthesis UK Asynchronous Forum, September 2008

One hot phase encoder (controller) Circuits synthesis UK Asynchronous Forum, September 2008

Outline Phase encoding Conditional partial order graphs Circuit synthesis Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder Conclusions and future work Outline UK Asynchronous Forum, September 2008

Binary phase encoder Data is normally given in binary form Binary phase encoder generates phase encoded symbols given binary encoded data Circuits synthesis UK Asynchronous Forum, September 2008

Outline Phase encoding Conditional partial order graphs Circuit synthesis Phase detector Matrix phase encoder One hot phase encoder Binary phase encoder Conclusions and future work Outline UK Asynchronous Forum, September 2008

Conclusions and future work The work presents a scalable approach for synthesis of multiple rail phase encoding circuits The approach uses the CPOG model in order to avoid exponential explosion of STG specifications due to duplication of events Phase encoders are synthesised for matrix, one hot, and binary source encodings, but the approach can be easily adapted for the other encodings e.g. m-of-n encoding The future work includes the development of automated synthesis tools based on the presented theoretical techniques Conclusions and future work UK Asynchronous Forum, September 2008

End Thank you! Questions? UK Asynchronous Forum, September 2008

STG specification explosion Handshake sequence 1 1 -> 2 2 -> 1 UK Asynchronous Forum, September 2008

STG specification explosion Handshake sequence 1 1 -> 2 2 -> 1 UK Asynchronous Forum, September 2008

STG specification explosion First scenario UK Asynchronous Forum, September 2008

STG specification explosion First scenario Event duplication! Second scenario UK Asynchronous Forum, September 2008

STG specification explosion + Reduces event duplication + Can be synthesised automatically (e.g. Petrify) – Difficult for manual design – Not visual – Contains a lot of additional places to track the choices – Very time consuming to generate UK Asynchronous Forum, September 2008

Thank you! More Questions? End Thank you! More Questions? UK Asynchronous Forum, September 2008