ETD parallel session March 18th 2010 Status of ETD D. Breton ETD parallel session March 18th 2010 D. Breton - SuperB Annecy Workshop - March 2010

Remarks about the former sessions Thursday afternoon, during the detector plenary session, the problem of the trigger latency was raised We agree that we now have to fix a maximum value for it in order to allow you to design your front-end electronics Based on experience and on what was implemented on LHC experiments, we decided to fix it to 4µs. This is a maximum value. It could be eventually lowered, but it allows us to envisage a powerful level 1 trigger. Yesterday, we had the ETD parallel session dedicated to front-end electronics it looks like things are converging in the definition of the internal architecture of subsystem electronics however, I feel like there are some discrepancies in the way the budget was calculated some people made a sharp calculation with little margin others seem to have taken wide “safety factors” I really think we should have a common philosophy (to be defined) D. Breton - SuperB Annecy Workshop - March 2010

D. Breton - SuperB Annecy Workshop - March 2010 Electronics costing EDIA Labor M&S TOTAL WBS Item (MM) (K$) (Keuro) 1.7 Electronics 994 18877 13103 342 6498 4511 10601 7359 35976 24973 1.7.1 SVT 11,0 Cost of SVT electronics estimated by Mauro 21,0 468 1.7.2 DCH 74 Cost of DCH electronics estimated by Giulietto 76 1390 1.7.3 PID Barrel (32k channels) 136 Cost of PID Barrel electronics estimated by Dominique 18 510 1.7.4 EMC 110,0 164,0 2271,5 1.7.5 IFR 37,5 Cost of IFR electronics estimated by Angelo 51,0 1239,0 1.7.6 Infrastructure 4 1.7.C 12 247 1.7.7 Systems Engineering AJR estimates 1.7.8 Hardware Trigger 97 Cost of Hardware Trigger electronics still based on BABAR's 532 1.7.9 ETD (without Trigger) 512 Cost of ETD electronics 990,0 D. Breton - SuperB Annecy Workshop - March 2010

D. Breton - SuperB Annecy Workshop - March 2010 Points to think of (1) In BABAR, dead-time (2.7µs) was introduced in the FCTS system after a level 1 trigger decision in order to simplify the front-end. this was not a problem because of the reasonable luminosity and low trigger rate (3kHz) In SuperB, at 150kHz, this would be an important source of dead-time The question remains: do we just leave the door fully open and put no restriction on the trigger ? Minimum distance between triggers would be only due to the trigger processors capacity to distinguish between consecutive events ~ 100ns The queue of previous events might be present in the following ones filtering this is a good job for the ROMs If the distance is smaller than the readout window (subdetector-specific), we’ll have to share the information between consecutive events (pile-up). we already showed that this is feasible in the common FEE recovering from pile-up is another good job for the ROMs Is any of these a problem for you ? D. Breton - SuperB Annecy Workshop - March 2010

D. Breton - SuperB Annecy Workshop - March 2010 Points to think of (2) Safety factors on dataflow: We would like to get the safety factors used for the readout link calculations for each subsystem and to understand what they are based on. Subsystems shouldn’t apply general safety margins like that on trigger rate => that one will be common to the whole experiment (looks like a factor 2 is required in view of luminosity upgrades) But they should for what concerns their channel occupancy (based on channel hit rate and trigger window width) Derandomizer depth: We have to simulate it (ensuring that no data could be lost after throttling in the derandomizer buffer even in the case of worst size events ?) ECS bandwidth: Subdetectors should think of the bandwidth they need to set up the FEE at startup or reload it because of radiation policy Set up time has to be reasonable (seconds) This is a key factor in defining the number of ECS links needed (10Mbits/s per links) D. Breton - SuperB Annecy Workshop - March 2010

D. Breton - SuperB Annecy Workshop - March 2010 16-channel TDC We are currently developing a TDC for the PID barrel 16 channels Steps of ~200ps from a 168MHz clock (3 x 56MHz), resolution of 70ps Very simple architecture: hit data is simply pushed on a parallel 16-bit bus it can be tailored to the targeted design in the companion FPGA almost nothing to program inside radiation tolerant design based on AMS CMOS 0.35µm technology this chip is available for any body interested inside SuperB D. Breton - SuperB Annecy Workshop - March 2010

D. Breton - SuperB Annecy Workshop - March 2010 Conclusion I guess there were some evolutions in your design during the workshop => don’t forget to update your section of the WP and budget We would like feedback from you about the points raised in the previous slides. We now enter the last phase of the TDR => we have to define our roadmap. => is there any new R&D needed ? WP is a great basis for TDR writing We’ll soon define the length of the different sections (might just a multiplication factor ?) We have to know when real chip and board design have to start if ever some of these points were crucial for the final schedule => Please think of it and tell us if some elements in your design do look crucial for you on this point of view Don’t forget about the long time necessary for series production and testing D. Breton - SuperB Annecy Workshop - March 2010