Systems Architecture II September 4, 1997 Systems Architecture II (CS 282-001) Lecture 5: Dealing with Pipeline Hazards* Jeremy R. Johnson *This lecture was derived from material in the text (Chap. 6). All figures from Computer Organization and Design: The Hardware/Software Approach, Second Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED). July 2, 2001 Systems Architecture II

Systems Architecture II September 4, 1997 Introduction Objective: In the previous lecture we saw the modifications necessary to the single-cycle implementation of MIPS to support pipelining. However, we ignored the possibility of pipeline hazards. In today’s lecture we show how to deal with pipeline hazards. A pipeline hazard is a situation where the next instruction cannot execute in the following clock cycle Topics Data hazards and forwarding Data hazards and stalls Control (branch) hazards stall and reducing the delay of branches dynamic branch prediction delayed branch Exceptions July 2, 2001 Systems Architecture II

Data Hazards and Forwarding Problem: Instruction depends on the result of a previous instruction still in the pipeline Example sub $2, $1, $3 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) July 2, 2001 Systems Architecture II

Timing Diagram with Data Dependencies July 2, 2001 Systems Architecture II

Systems Architecture II Hazard Detection 1a) EX/MEM.RegisterRd = ID/EX.RegisterRs 1b) EX/MEM.RegisterRd = ID/EX.RegisterRt 2a) MEM/WB.RegisterRd = ID/EX.RegisterRs 2b) MEM/WB.RegisterRd = ID/EX.RegisterRt sub $2, $1, $3 and $12, $2, $5 (1a) or $13, $6, $2 (2b) add $14, $2, $2 (no hazard) sw $15, 100($2) (no hazard) July 2, 2001 Systems Architecture II

Systems Architecture II Forwarding July 2, 2001 Systems Architecture II

Pipelined Datapath with Forwarding July 2, 2001 Systems Architecture II

Control for Hazard Detection and Forwarding EX hazard: if (EX/MEM.RegWrite) and (EX/MEM.RegisterRd  0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs) then ForwardA = 10 MEM hazard: if (MEM/WB.RegWrite) and (MEM/WB.RegisterRd  0) and (EX/MEM.RegisterRd  ID/EX.RegisterRs) and (MEM/WB.RegisterRd = ID/EX.RegisterRs) then ForwardA = 01 July 2, 2001 Systems Architecture II

Datapath with Control for Forwarding July 2, 2001 Systems Architecture II

Systems Architecture II Example 1 July 2, 2001 Systems Architecture II

Systems Architecture II Example 2 July 2, 2001 Systems Architecture II

Systems Architecture II Example 3 July 2, 2001 Systems Architecture II

Systems Architecture II Example 4 July 2, 2001 Systems Architecture II

Data Hazards and Stalls Problem: Sometimes a data dependency can not be resolved with forwarding (e.g. a load dependency) July 2, 2001 Systems Architecture II

Inserting Stalls into the Pipeline If (ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))) stall the pipeline (insert nop by setting control = 0) July 2, 2001 Systems Architecture II

Datapath with Control for Stalls July 2, 2001 Systems Architecture II

Systems Architecture II Example 1 July 2, 2001 Systems Architecture II

Systems Architecture II Example 2 July 2, 2001 Systems Architecture II

Systems Architecture II Example 3 July 2, 2001 Systems Architecture II

Systems Architecture II Example 4 July 2, 2001 Systems Architecture II

Systems Architecture II Example 5 July 2, 2001 Systems Architecture II

Systems Architecture II Example 6 July 2, 2001 Systems Architecture II

Systems Architecture II Branch Hazards Problem: An instruction must be fetched every cycle yet the decision of whether to branch doesn’t occur until MEM pipeline stage July 2, 2001 Systems Architecture II

Reducing the Delay of Branches Assume branch not taken. Reduce cost if branch taken, which implies fewer instructions need to be flushed. July 2, 2001 Systems Architecture II

Systems Architecture II July 2, 2001 Systems Architecture II

Systems Architecture II July 2, 2001 Systems Architecture II

Systems Architecture II Loop Prediction Try to predict whether or not a branch will be taken Use branch table to keep track if branch was taken previously 2-bit prediction improves prediction rate (e.g. loop) July 2, 2001 Systems Architecture II

Systems Architecture II Branch Delays Branch Delay Always execute instruction after branch Rely on compiler to put safe instruction in branch delay slot July 2, 2001 Systems Architecture II

Systems Architecture II Exceptions Problem: Another control hazard is an exception (e.g. arithmetic overflow). In this case we need to transfer control to an exception handler. Need to flush pipeline. July 2, 2001 Systems Architecture II

Systems Architecture II July 2, 2001 Systems Architecture II

Systems Architecture II July 2, 2001 Systems Architecture II

Performance Improvement Problem: Assume 2ns for memory access, ALU op, and 1ns for register file access. Assume 1/2 load instructions immediately followed by instruction using result. Branch delay for misprediction is 1 cycle and 1/4 of the branches are mispredicted. Assume full clock delay on all jumps. Assume 22% loads, 11% stores, 49% R-format, 16% branches, and 2% jumps. What is the CPI for pipelined implementation? What is the performance gain over the single cycle implementation? What is the performance gain over the multicycle implementation? July 2, 2001 Systems Architecture II