Ideal Scaling of MOSFETs A set of ideal scaling laws have been proposed by Dennard and Gaensleen. The basic concept is to minimize a MOSFET while keeping the E-fields in the device approximately constant. (This is a reasonable concept since, if E-fields are reduced, carrier velocity will decrease. Large E-fields can cause materials to reach their limits such as breakdown voltages, etc.) I/S VG/S V/S

These relationships are true to first order since

Note that in reality, fbi, fms, and fB do not scale. Since fbi » 0 Note that in reality, fbi, fms, and fB do not scale. Since fbi » 0.8Volts and 2fB » 0.7-1.5 volts, we clearly cannot neglect them, especially if applied biases are scaled to this range. However, in n+-polysilicon gate NMOS, the fms term approximately cancels that of the 2fB term. Are these scalings realistic? Since the publishing of the paper in 1974, we see the following trend: Parameter 1994 1999 2007 1. Layout Density (gates/mm2) 104 105 108 2. Speed Power Product (pj) 0.01 10-4 10-8 3. Gate Delay (ps) 100 12 0.1 4. Power supply (V) 3.3 1.8 1.0 5. Channel Length (nm) 350(250) 180( 120) 45(30) 6. Oxide Thickness (tox(Å) ) 23

Problem with Ideal Scaling A number of factors were neglected in the above analysis. Many of these become increasingly important in submicron-size devices.

Supply Voltage vs. Gate Length Scaling 0.85/generation 0.65/generation The E-field increases rapidly and leads to many performance and reliability problems

What is the Moore’s Law? Not a scientific formulation yet has been surprising accurate in predicting the “future” back in 1965

Why Scaling? MOSFETs need to be scaled to smaller dimensions results in higher performance leads to lower power consumption MOSFET delay times have decreased by more than 30% per generation resulting in doubling of mP performance every 2 years

Scaling for the Economics In 2003, $0.01 bought you 100,000 transistors Increased transistor counts and thus cheaper transistors More performance per dollar