CMOS Layers n-well process p-well process Twin-tub process.

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Presentation transcript:

CMOS Layers n-well process p-well process Twin-tub process

MOSFET Layers in an n-well process p-substrate n+ p+ n-well Gate NMOS PMOS FOX MOSFET Layers in an n-well process

Layer Types p-substrate n-well n+ p+ Gate oxide Gate (polycilicon) Field Oxide Insulated glass Provide electrical isolation

Top view of the FET pattern PMOS NMOS NMOS PMOS n+ n+ p+ p+ n-well

Metal Interconnect Layers Metal layers are electrically isolated from each other Electrical contact between adjacent conducting layers requires contact cuts and vias

Metal Interconnect Layers Ox3 Via Metal2 Active contact Ox2 Metal1 Ox1 p-substrate n+ n+ n+ n+

Interconnect Layout Example Gate contact Metal1 Metal2 Metal1 MOS Active contact

Designing MOS Arrays A B C y x A B C y x

Parallel Connected MOS Patterning x x A B A B X X X y y

Alternate Layout Strategy x x X X A B A B X X y y

Basic Gate Design Both the power supply and ground are routed using the Metal layer n+ and p+ regions are denoted using the same fill pattern. The only difference is the n-well Contacts are needed from Metal to n+ or p+

The CMOS NOT Gate Contact Cut Vp Vp X n-well X X X Gnd Gnd

Alternate Layout of NOT Gate Vp Vp X X X X Gnd Gnd

NAND2 Layout Vp Gnd Vp X X X X X Gnd

NOR2 Layout Vp Gnd Vp X X X X X Gnd

NAND2-NOR2 Comparison X Vp Gnd X Vp Gnd MOS Layout Wiring

General Layout Geometry Vp Shared drain/ source Individual Transistors Shared Gates Gnd

Graph Theory: Euler Path Vp x Vertex b c x a Edge Out y c y Vertex a b Gnd

Stick Diagram

Stick Diagrams Cartoon of a layout. Shows all components. Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc.

Stick Diagrams Metal poly ndiff pdiff Can also draw in shades of gray/line style.

Stick Diagrams Buried Contact Contact Cut

5 V Dep Vout Enh 0V 0 V Vin 5 v 5 v Vin

Stick Diagram - Example I NOR Gate OUT B A

Stick Diagram - Example II Power A Out C B Ground

Points to Ponder be creative with layouts sketch designs first minimize junctions but avoid long poly runs have a floor plan plan for input, output, power and ground locations

The End