Implementing Combinational

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Presentation transcript:

Implementing Combinational ECE 448 Lab 2 Implementing Combinational Logic in VHDL ECE 448 – FPGA and ASIC Design with VHDL George Mason University

Agenda for today Part 1: Introduction to Lab 2 Implementing Combinational Logic in VHDL. Part 2: Example: miniALU. Part 3: Variable Rotator. Part 4: Hands-on Session: Simulation Using ModelSim. Part 5: Demos of Lab 1.

Implementing Combinational Part 1 Introduction to Lab 1 Implementing Combinational Logic in VHDL

Interface of ALU 8 A ALU B OPCODE 4 Y X Z Cout V F_active Cin

Interface of ALU

Table of Operations

Block Diagram

Example of a Problem Similar to Task 1 Part 2 Example: Mini ALU Example of a Problem Similar to Task 1

opcode 4 4 A 4 4 Mini ALU R B 4 M

Mnemonic Operation Opcode ADDAB R= A + B 0000 ADDAM R = A + M 0001 SUBAB R = A - B 0010 SUBAM R = A - M 0011 NOTA R = NOT A 0100 NOTB R = NOT B 0101 NOTM R = NOT M 0110 ANDAB R = A AND B 0111 ANDAM R = A AND M 1000 ORAB R = A OR B 1001 ORAM R = A OR M 1010 XORAB R = A XOR B 1011 XORAM R = A XOR M 1100

Block diagram

Example of a Problem Similar to Bonus Task Part 3 Variable Rotator Example of a Problem Similar to Bonus Task

Function C = A <<< B A – 4-bit data input B – 2-bit rotation amount

Interface A 4 2 B 4 C

Block diagram C

Fixed Rotation in VHDL SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0); A(3) A(2) A(1) A(0) A A<<<1 Internal signals are from DUT. Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors. Many architectures can be tested by inserting more for DUT:TestComp use entity work.TestComp(archName) statmetns “work” is the name of the library that “TestComp” is being compiled to. The “DUT” tag is required. ArotL A(2) A(1) A(0) A(3) ArotL <= A(2 downto 0) & A(3);

Simulation Using ModelSim Part 4 Hands-on Session Simulation Using ModelSim