Seoul National University Pipelining Basics

Sequential Processing Seoul National University Sequential Processing

Seoul National University Pipelined Processing

Basic Steps of Execution Seoul National University Basic Steps of Execution 1. Instruction fetch step ( F ) 2. Instruction decode/register fetch step ( D ) 3. Execution/effective address step ( E ) 4. Memory access (M) 5. Register write-back step (W)

Pipelined Instruction Execution Seoul National University Pipelined Instruction Execution Sequential Execution Pipelined Execution addq %rcx, %rax subq %rdx, %rbx andq %rdx, %rcx

Basic Pipeline F D E M W Clock number 1 2 3 4 5 6 7 8 9 Seoul National University Basic Pipeline Clock number Instruction number 1 2 3 4 5 6 7 8 9 Instruction i F D E M W Instruction i + 1 Instruction i + 2 Instruction i + 3 Instruction i + 4

Major Hurdles of Pipelining Seoul National University Major Hurdles of Pipelining Structural Hazard Data Hazard Control Hazard

Structural Hazard F D E M W F D E M W F D E M W F D E M W F D E M W Seoul National University Structural Hazard F D E M W F D E M W F D E M W F D E M W Clock number Instruction number 1 2 3 4 5 6 7 8 9 Load Instruction F D E M W Instruction i + 1 Instruction i + 2 Instruction i + 3 Instruction i + 4

Solutions to Structural Hazard Seoul National University Solutions to Structural Hazard Resource Duplication example Separate I and D caches for memory access conflict Multi-port register file for register file access conflict

Data Hazard (RAW hazard) Seoul National University Data Hazard (RAW hazard) addq %rdx, %rax subq %rax, %rcx F D E M W F D E M W Time

Solutions to Data Hazard Seoul National University Solutions to Data Hazard Freezing the pipeline (Internal) Forwarding Compiler scheduling

Freezing The Pipeline ALU result to next instruction Seoul National University Freezing The Pipeline ALU result to next instruction Load result to next instruction F D E M W addq %rdx, %rax stall stall stall F D subq %rax, %rcx F D E M W mrmovq 0(%rdx), %rax addq %rdx, %rax stall stall stall F D

(Internal) Forwarding Seoul National University (Internal) Forwarding ALU result to next instruction (Stall X) Load result to next instruction (Stall 1) F D E M W addq %rdx, %rax F D E M W subq %rax, %rcx F D E M W mrmovq 0(%rdx), %rax stall F D E M addq %rdx, %rax Load interlock

For 5-stage pipeline, 3 cycle penalty 15% branch frequency. CPI = 1.45 Seoul National University Control Hazard Caused by PC-changing instructions ((conditional/unconditional) Jump, Call/Return) (Example) Branch Instruction F D E M W Branch successor stall Branch successor + 1 Branch successor + 2 Branch successor + 3 Branch successor + 4 Branch successor + 5 For 5-stage pipeline, 3 cycle penalty 15% branch frequency. CPI = 1.45

Branch Prediction Predict-taken ~60% success rate Seoul National University Branch Prediction Predict-taken Taken branch instruction F D E M W Branch target Branch target + 1 Branch target + 2 Branch target + 3 Untaken branch instruction F D E M W Branch target idle Branch target + 1 Branch target + 2 Untaken branch instruction + 1 ~60% success rate