EE108b Review Session February 2nd, 2007 Daxia Ge

Admin Quiz #1 Office hours Tuesday, 7 – 9 pm Bldg 420-041 (look on website for map and directions) Covers lectures 1-7 (no pipelining) One page of notes, green card, calculator Office hours No lecture Tuesday! Professor Kozyrakis will have office hours during that time Sunday 4:00pm (Daxia), Monday 3:00pm (Drew), Tuesday 1:00pm (Yi)

Quiz #1 (lectures 1-7) MIPS assembly language Performance Software Execution time Amdahl’s Law Benchmarks Software Compiling process Optimizations and common techniques Processor Single cycle building blocks

Translation hierarchy Compiler: High-level language in, assembly out Performs assembly code optimization Assembler: Assembly in, machine code out Expands macros and pseudoinstructions Outputs object file (machine code) Linker: Resolves references Libraries Loader: initializes the program CPU: execution

Optimizations High Level -close to the source -loop inversion / loop unrolling -> why useful? Local - Constant folding (combining constants and arithmetic operations) - Constant propagation - Strength reduction - Common sub-expression elimination - Induction variable elimination - Leaf procedures – no need for stack - Registers! Global - Much the same as local, but not confined to basic blocks Processor dependent - knowledge of specific architecture (cache line size, L1, L2) - ie AMD Opteron flag for gcc

MIPS processor The basic ALU Combinational blocks Gate delays 5 steps in carrying out an instruction: Instruction fetch - Execution Instruction decode - Data write back Data load Strongly tied to instruction format in machine code

Pipelining Improve resource utilization Increases throughput Data and control signals have to be propagated

Example Problem: Processor Design It happens quite often that we wish to index through and access each element of an array. Absent from MIPS, but present in other assembly languages/instruction sets are load/store commands which also increment the indexing register. For example, lwinc $rt, offset($rs) would perform the normal load and subsequently increment $rs by 4. Please either describe in words, or show in the figure below, all necessary modifications needed to support these instructions in the single-cycle MIPS processor discussed in lecture. Remember the load/store instruction format (unchanged for lwinc): load / store Rs Rt Offset 31:26 25:21 20:16 15:0

Example problem: Solution The datapath requires an additional ALU to increment the content of the $ rs register (Read data 1) by 4. The output of this is fed back to the register file, which needs a second write port because two writes to the register are required in a single cycle. The new write port will be controlled by a new signal, "Write 2." We assume that the destination register for the second write is always the same as Read register 1 ($ rs). This way "Write 2" indicates that there is second write to register file to the register identified by "Read register1," and the data is fed through Write data 2. Incorrect answers include adding a second register file since then the contents of the two would have to be kept consistent.