ECE 352 Digital System Fundamentals SRAM Design In this presentation, we will look at how static RAM devices are designed.

Both selects must be 1 to select the cell SRAM Cell Augment a D Latch Tristated output Multiple enable signals Both selects must be 1 to select the cell must be true for a read row select bit select To construct an SRAM, we start with a single SRAM cell, which will store a single bit of data. It is basically a D latch with some additional logic. The cell has a tristate data output, so the output buffer must be enabled to read the cell data. There are two enables, the row select and the bit select. Both of these must be 1 to select the cell. We’ll talk more about how we use these enables shortly. To update the data in the latch, its control input must be 1, so the cell must be enabled AND the read/not-write signal must be 0 to perform a write. data in data out (tristated) RD/ WR 0 = write 1 = read must be true for a write

SRAM Bitslice data in (DIN) RD/ WR row selects bit select As with any complicated design, SRAMs are designed hierarchically. A bitslice is a vector of interconnected SRAM cells that share a common data in and data out. We select individual cells within a bitslice using the row select, which will come from a decoder to ensure exactly one of these signals is 1 at any given time. The decoder and the tristate buffers within the cells together form a distributed multiplexer. The bit select will select the entire bitslice (hence the name), so it is shared by all cells within the bitslice. The cells also have a common read/not-write input. We will use bitslices as building blocks to create SRAM devices. bit select data out (DOUT)

4 × 1 SRAM row selects Contains a single bitslice with four rows Data word is only 1 bit wide Plus an address decoder to select the location 4 locations  2 address bits Bit select = chip select (CS) Bitslice is enabled when SRAM is enabled First we’ll create a 4 x 1 SRAM. That means that the SRAM has 4 locations, each of which store a single bit. So we create a single bitslice with four rows. In this diagram, we do not show the individual gates within each SRAM cell. To simplify our diagram, we abstract away the inner details of the bitslice, hiding many of the signal connections. All the signals are still present, just not all of them are shown. We still show the row selects, which we connect to the output of a decoder that will enable one row based on the address. Since this SRAM has 4 locations, it requires a 2-bit address, and a 2-to-4 address decoder. The decoder is also called a “row decoder” because it provides the row select outputs. The chip select is a global enable for the SRAM device, so we use it to enable the bitslice. We select an individual cell within this SRAM by providing its address to enable its row select, and setting CS to 1 to enable the bitslice. We also need to connect the read/not-write signal and the data in and out to the bitslice. DI R/ W CS DO

4 × 2 SRAM Similar to 4 × 1 SRAM design… But with two bitslices Example: A[1:0] = 01 Similar to 4 × 1 SRAM design… But with two bitslices Data word is 2 bits wide Bit select = CS Both bitslices enabled when SRAM is enabled Each bitslice contains one bit of every word in the memory A bitslice is a vertical slice of the words ADDRESS 01 We can create a 4 x 2 SRAM that stores four 2-bit words, by creating a design similar to the 4 x 1 SRAM we showed, but with two bitslices – one per bit position in our data word. We connect the chip select to the bit select input of both bitslices to enable both of them whenever the device is enabled. The bitslice on the left contains bit 1 of each of the four data words, and the bitslice on the right contains bit 0 of each of the words. So, if the address input equals 1, the decoder selects row 1. If the chip select is enabled, then these two cells are enabled. This means they store the 2-bit word at address 1. CS R/ W DI[1] DI DO[1] DO DI[0] DO[0] bitslice 1 bitslice 0

Memory Design: Simple Case Number of rows = number of words Each bitslice contains one bit of every word in the memory For example, bitslice 0 contains bit 0 of each word Decode the memory address to create the row select signals At most one row select can be active at any time or there is contention! Connect bit select input of all bitslices to CS so they are all enabled when the SRAM is enabled This will not be the case later when we examine more complex memory designs… The designs we’ve shown so far represent the simple case of SRAM design, where each word is stored in its own row in memory, and the number of bitslices is equal to the data word size. We have only one decoder, which decodes the address into the row select signals. When the memory is enabled, we enable all bitslices so that we can access entire words of data at a time. Soon we will look at more complex designs where some of these guidelines change – but not just yet.

Memory Parameters If you know enough of the design parameters, you can figure out the others… Total capacity = <# of words> × <word size> Number of address bits = ceil(log2(<# of words>)) Number of rows = <# of words> Row decoder size = <# of address bits>–to–<# of rows> No column decoder (always one column of words) Number of bitslices = <word size> First we will look at how, for this simple design case, we can calculate required memory design parameters based on a given subset of the parameters. Here are a few general rules we will use in the examples that follow. Essentially, if we know enough of the parameters, we can calculate the others. Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words)

Examples If you know enough of the design parameters, you can figure out the others… single column of words Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 13 : 8 K 8 K 1 32 None 256 Kbits 8 K = 23 × 210 = 213 32 × 8 K = 25 × 213 = 218 bits We will work through three examples. Our first example is an 8K x 32 SRAM. In each of the three examples, we will have a single column of words, so do not need a column decoder. We’ll talk more about what that means later. We can calculate the capacity by multiplying the word size times the number of words and we get 256 Kbits. If we rewrite the number of words as a power of 2, we can determine the number of address bits that we need. For now, the number of rows is equal to the number of words, and the number of bitslices is equal to the word size. We can determine the size of the row decoder because it must have as many outputs as there are rows, and in this case, as many inputs as the number of address bits. Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words)

Examples If you know enough of the design parameters, you can figure out the others… Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 13 : 8 K 8 K 1 32 None 256 Kbits 8 bits 32 5 5 : 32 32 1 8 None 256 bits In our second example, we know that we have 5 address bits and 8 bitslices. And once again, we have a single column of words. Our address size tells us the number of words, as well as the size of the row decoder, which then gives us the number of rows. Again, our word size is equal to the number of bitslices. Last, we can determine the capacity either by multiplying the number of words by the size of the words, or, as we show here, by multiplying the number of rows by the number of bitslices. Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words)

Examples If you know enough of the design parameters, you can figure out the others… Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 13 : 8 K 8 K 1 32 None 256 Kbits 8 bits 32 5 5 : 32 32 1 8 None 256 bits In our third example, we know the capacity and the size of the row decoder, and that we have a single column of words. The number of row decoder inputs is equal to the address size, and the number of row decoder outputs is equal to the number of rows, which is also equal to the number of words. We can divide the capacity by the number of words to get the word size, which is also equal to the number of bitslices. 16 bits 64 6 6 : 64 64 1 16 None 1 Kbit Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words)

Examples If you know enough of the design parameters, you can figure out the others… Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 13 : 8 K 8 K 1 32 None 256 Kbits 8 bits 32 5 5 : 32 32 1 8 None 256 bits Remember, some of these calculations only work for the simple case where we have a single column of words, one word per row. 16 bits 64 6 6 : 64 64 1 16 None 1 Kbit Some of these calculations are only valid for this style of memory (single column of words, number of rows = number of words)

Increasing Number of Words As we increase the number of words in the memory, the address decoder gets bigger Bigger decoder  longer paths  slower Instead of organizing the memory as a linear array, organize it as a 2D grid of (multi-bit) words Break the address decoder into separate row and column decoders One problem with our simple SRAM design model is that it is not scalable. As memories get larger, the address decoding delay increases. To deal with this problem, we’re going to change the organization of the memory.

Coincident Selection Technique to reduce decoder size by breaking up the selection process into two parts A decoder to select the row (row decoder) A decoder to select the column (column decoder) A column is a logical group of bitslices that supplies all of the bits required by the memory’s data width Each column may be made up of multiple bitslices! # bitslices per column (of words) = data width A memory cell is only selected if it is selected by both the row decoder and the column decoder We call this design technique “coincident selection”. Words are arranged in a 2D grid, and we have two smaller decoders instead of one big one. We select a row using part of the address, and select a column using the rest of the address. Only the cells for one word can be selected by both the row and column decoders at any given time, so each word still has a unique address.

Coincident Selection Example We will show two ways to build a 16 × 1 SRAM Too small to actually worry about the organization… This does become critical for very large SRAMs! 1 1 One column of 1-bit words Four columns of 1-bit words 1 One bitslice Let’s look at what this means for a 16 x 1 SRAM. Conceptually, this SRAM has a single column of 16 different 1-bit locations. We could also build it that way, with a single bitslice that has 16 rows. Or, we could take the same memory and reorganize it to have four columns of 1-bit words, by creating four bitslices, each with four rows. Four bitslices 1 Sixteen rows Four rows 1

Single-Column 16 × 1 SRAM 4 address bits 4:16 row decoder 16 rows  16 row decoder outputs Decodes entire address Each output enables one 1-bit word No column decoder Single bitslice Enabled by chip select A[3] A[2] A[1] A[0] Let’s take a closer look at these two designs for a 16 x 1 SRAM. The first one had a single bitslice. The four address bits are the inputs to the 4:16 row decoder whose outputs each enable one of the memory cells. There is no column decoder, and the bitslice is enabled by the chip select. DI R/ W CS DO

Multi-Column 16 × 1 SRAM 4 address bits 2:4 row decoder 4 rows  4 row decoder outputs Decodes 2 address bits Each output enables four 1-bit words 2:4 column decoder Decodes remaining address bits Four columns, one bitslice each Each decoder output enables one bitslice Enabled by chip select A[1] A[0] DI DO R/ W Our second design rearranges the same 16 bits of storage into a 2D grid. We still have four address bits, because logically the model is the same. This time, however, we only have four rows, so we have a 2:4 row decoder, which uses two bits of the address. The other two address bits are used by the column decoder, which means we must have four columns of 1-bit words (one column per output of the column decoder). This decoder is enabled by the chip select; if CS is 0, no bitslices are selected. If CS is 1, only the cell selected by both the row and column decoders will be selected. A[3] A[2] CS

Coincident Selection Example How can we arrange the bits in an 8 × 2 SRAM? We could also do four columns (eight total bitslices) and two rows… Or eight columns (16 total bitslices) and one row… One column of 2-bit words Two columns of 2-bit words 1 1 1 1 We’ll look at another example with the same total capacity: an 8 x 2 SRAM, which has eight locations, each 2 bits wide. We could build it like the conceptual model, with a single column of 2-bit words, using two bitslices that each have eight rows. Or, we could take the same memory and reorganize it to have two columns of 2-bit words, which requires four bitslices that each have four rows. Alternately, we could have designed this with four columns and two rows, or eight columns and one row. The product of rows and columns must equal the number of words. Two bitslices Four bitslices 1 1 Eight rows Four rows

Single-Column 8 × 2 SRAM 3 address bits 3:8 row decoder Example: A[2:0] = 110 3 address bits 3:8 row decoder 8 rows  8 row decoder outputs Decodes entire address Each output enables one 2-bit word No column decoder Two bitslices Both enabled by chip select A[2] A[1] A[0] ADDRESS 110 The single-column 8 x 2 SRAM has a row decoder that decodes all three address bits. There is no column decoder, and both bitslices are enabled by the chip select. If we use an address equal to 6, the row decoder will select both cells in row 6. If CS is 1, the two bits of storage for address 6 will be selected. R/ W CS DI[1] DO[1] DI[0] DO[0]

Multi-Column 8 × 2 SRAM 3 address bits 2:4 row decoder Example: A[2:0] = 110 3 address bits 2:4 row decoder 4 rows  4 row decoder outputs Decodes 2 address bits Each output enables two 2-bit words 1:2 column decoder Decodes remaining address bits Two columns, two bitslices each Each decoder output enables two bitslices Enabled by chip select A[1] A[0] ADDRESS 110 DI DO R/ W In the multi-column 8 x 2 SRAM, the SRAM cells are rearranged. We still have three address bits, but only four rows, so we have a 2:4 row decoder, which uses two bits of the address. The remaining address bit is used by the column decoder, which means we have two columns of 2-bit words (one column per column decoder output). Here, our word size is 2 bits, so each column decoder output enables two bitslices – the two bitslices within the selected column of words. Like before, the column decoder is enabled by the chip select. Let’s look at what happens in this design when we use an address equal to 6. The lower two bits of the address are 10, which selects both words in row 2. If the column decoder is enabled by the chip select, it enables the left two bitslices because A[2] is equal to 1. The two selected cells are the ones that store the 2-bit word at address 6. A[2] CS

Coincident Selection Notes The logical view (view from outside) is the SAME Does not change how the memory is used The capacity is still <# of words> × <word size> Internally: The # of rows is no longer equal to the # of words The # of bitslices is no longer equal to the word size Each column has a number of bitslices equal to the word size Each column decoder output goes to the same number of bitslices as before… Equal to the number of bits per data word Although we reorganize the internal structure of the SRAMs when we use coincident selection, the external view is the same. From the outside, we can still think of it as a 1D array that is indexed by the address. The capacity is still based on the number of words and the size of each word. However, the internal structure, and the parameters used to create it, are computed a bit differently from the single-column model. This can look tricky at first, but makes sense if you think about the way the bits have been rearranged. Remember: bitslice = vertical slice of bits within column of words!

Examples If you know enough of the design parameters, you can figure out the others… two columns of words Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 8 K = 23 × 210 = 213 32 × 8 K = 25 × 213 = 218 bits 13 – 1 = 12 We’ll look at three examples of computing the parameters for multi-column SRAM designs. In the first, we will create an SRAM that stores 8K words that are 32 bits each, in two columns. Just like before, we can compute the total capacity from the word size and number of words – that hasn’t changed. The number of words still tells us how many address bits we need. If we have two columns, we need a column decoder with two outputs. Each column has as many bitslices as bits in the word, so the number of bitslices is the word size times the number of columns. If we used one bit of the address for the column decoder, we must use the remaining 12 bits for the row decoder. Finally, the SRAM will have as many rows as row decoder outputs.

Examples If you know enough of the design parameters, you can figure out the others… Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 2 bits 32 5 3 : 8 8 4 8 2 : 4 64 bits In the second example, we need to design a memory with 5 address bits, 4 columns, and 8 bitslices. Our column decoder needs as many outputs as there are columns. The address size tells us the number of words, and the number of bitslices per column is equal to the word size. If 2 of our 5 address bits are used for the column decoder, the other 3 must be used by the row decoder. The row decoder size tells us the number of rows. We multiply the bitslices by rows to get the total capacity, which is also equal to the number of words times the word size. In this case, the SRAM cells are arranged in a square array because the width (the number of bitslices) is equal to the height (the number of rows). The multi-column designs we showed earlier for the 16 x 1 and 8 x 2 SRAMs were also arranged as square arrays.

Examples If you know enough of the design parameters, you can figure out the others… Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 2 bits 32 5 3 : 8 8 4 8 2 : 4 64 bits For the last example, we are given the size of the row decoder, the number of columns, and the total capacity. We again compute each of the missing parameters based on the information that we were given – we just have to do it step-by-step. 2 bits 512 9 6 : 64 64 8 16 3 : 8 1 Kbit 210 / 29 = 2

Examples If you know enough of the design parameters, you can figure out the others… Word Size Num Words Addr Size Row Decode Num Rows Num Cols Num Bitslices Col Decode Total Capacity 32 bits 8 K 13 12 : 4 K 4 K 2 64 1 : 2 256 Kbits 2 bits 32 5 3 : 8 8 4 8 2 : 4 64 bits Mainly, we need to remember the relationships between these parameters, which is easy if we understand the structures involved and how they are used together. It then boils down to applying a little bit of algebra and geometry. 2 bits 512 9 6 : 64 64 8 16 3 : 8 1 Kbit

ECE 352 Digital System Fundamentals SRAM Design This concludes our video on SRAM device design.