IH2020 Info day on ICT WP 2019 - Photonics topics Brussels, 18 January 2019 IH2020 Info day on ICT WP 2019 - Photonics topics Photonics Proposals Lessons learned from earlier photonics calls in H2020 Christoph Helmrath

DO NOT FORGET Respect the page limitations in your proposal – RIA/IA 70 pages – CSA 50 pages. Do not put information relevant to sections B1 to B3 in sections B4 or B5 Make sure you address and submit under the correct topic Read carefully the work programme/call texts including introduction text and address all the requirements Read carefully the proposal template and its instructions and guidance – and implement them properly, be aware of the evaluation criteria Check SME status, SME budget is potentially a ranking criterion (in case of ties) Re-submission: high risk of failure if not truly addressing the new call Get somebody who was not involved to read your proposal "it was so obvious to the proposers what they were planning that they forgot to mention it“ Check the PDF conversion of your proposal Do not wait until the last minute (= last day) to submit Don't focus only on those parameters which are to be improved (higher speed, higher bandwidth, lower energy consumption, ...) but also on other parameters, e.g., on a module or subsystem level (not on a chip level only)  this is also linked to the "progress beyond the state of the art" For example, if a chip enables much higher operation speed, the cost of related driving electronics is of high relevance and too high driving electronics cost or the need of an RF package could completely counterbalance or undo any possible advantage . Therefore. Comparisons should also be made with SoA at subsystem, module level Promising exploitation potential can be expected if an in-depth comparison between commercially available solutions and a module, subsystem, ... based upon the targeted project results does suggest such potential. However, there is one additional ‘caveat’ in this respect: Comparisons should be made not only with commercial solutions available today, but extrapolate the performance of current commercial solutions to what their expected performance will/might be in about four (or even more) years ahead (“Moore’s law” and similar dependences for optoelectronic chips)

IPR Addressing (… and assessing) IPR Issues Do not postpone IPR issues to the consortium agreement but outline in the proposal your strategy for management of IPRs and their protection For example: Check existing patents – state whether they can be a barrier to exploitation and how you intend to overcome it  Freedom to Operate Clearly outline the expected IPRs from your project (capable of commercial/industrial exploitation) Outline how you will handle / share background information and expected project results and how do you envisage to protect your results

Exploitation strategies Strong exploitation strategies Do not provide market potential in generic terms on possible sales. Do not postpone exploitation strategies until the project starts. Specify which fraction of these markets expected project outcomes will address Include a reasonable comparison with competitors in the same technology and with solutions of competing technologies Show where / why there is real competitive advantage and exploitation potential; identify the applications and business cases - foresee to regularly monitor the market Provide exploitation strategies /plans that are: well thought-through, complete, and concrete enough (including possibly measurable targets) coherent and consistent with the proposed implementation Don't focus only on those parameters which are to be improved (higher speed, higher bandwidth, lower energy consumption, ...) but also on other parameters, e.g., on a module or subsystem level (not on a chip level only)  this is also linked to the "progress beyond the state of the art" For example, if a chip enables much higher operation speed, the cost of related driving electronics is of high relevance and too high driving electronics cost or the need of an RF package could completely counterbalance or undo any possible advantage . Therefore. Comparisons should also be made with SoA at subsystem, module level Promising exploitation potential can be expected if an in-depth comparison between commercially available solutions and a module, subsystem, ... based upon the targeted project results does suggest such potential. However, there is one additional ‘caveat’ in this respect: Comparisons should be made not only with commercial solutions available today, but extrapolate the performance of current commercial solutions to what their expected performance will/might be in about four (or even more) years ahead (“Moore’s law” and similar dependences for optoelectronic chips)

Value chain and commitment Cover the value chain as appropriate, demonstrate commitment In general, successful proposals covered all or major part of value chain included relevant and committed players from industry included relevant and committed end-users Commitment means: Show engagement in the expected project outcomes by having a substantial participation in "important" project work packages and/or by leading essential project tasks Include a larger effort during the proposal preparation to either include partner(s) with clearer commercialisation ability or to incorporate activities in the project for ensuring commercialisation  Identify in the project possible product owner(s)! Don't focus only on those parameters which are to be improved (higher speed, higher bandwidth, lower energy consumption, ...) but also on other parameters, e.g., on a module or subsystem level (not on a chip level only)  this is also linked to the "progress beyond the state of the art" For example, if a chip enables much higher operation speed, the cost of related driving electronics is of high relevance and too high driving electronics cost or the need of an RF package could completely counterbalance or undo any possible advantage . Therefore. Comparisons should also be made with SoA at subsystem, module level Promising exploitation potential can be expected if an in-depth comparison between commercially available solutions and a module, subsystem, ... based upon the targeted project results does suggest such potential. However, there is one additional ‘caveat’ in this respect: Comparisons should be made not only with commercial solutions available today, but extrapolate the performance of current commercial solutions to what their expected performance will/might be in about four (or even more) years ahead (“Moore’s law” and similar dependences for optoelectronic chips) Device / Materials Providers Equipment Providers Components Manufacturers Systems Integrators / Systems Vendors End-users

Pilot lines The key elements are amongst others: Open access Industrially relevant business cases Well elaborated plan addressing the long term-sustainability Credible strategy for future high volume production

Coordination and Support Actions Often very clear on the objectives (as stated in work programme text) but very generic about what they will do. Proposals should Be very specific on how exactly the action will serve the target group Describe any links to ongoing actions in the field to ensure complementarity, coordination and added value. Don't focus only on those parameters which are to be improved (higher speed, higher bandwidth, lower energy consumption, ...) but also on other parameters, e.g., on a module or subsystem level (not on a chip level only)  this is also linked to the "progress beyond the state of the art" For example, if a chip enables much higher operation speed, the cost of related driving electronics is of high relevance and too high driving electronics cost or the need of an RF package could completely counterbalance or undo any possible advantage . Therefore. Comparisons should also be made with SoA at subsystem, module level Promising exploitation potential can be expected if an in-depth comparison between commercially available solutions and a module, subsystem, ... based upon the targeted project results does suggest such potential. However, there is one additional ‘caveat’ in this respect: Comparisons should be made not only with commercial solutions available today, but extrapolate the performance of current commercial solutions to what their expected performance will/might be in about four (or even more) years ahead (“Moore’s law” and similar dependences for optoelectronic chips)

Impact, Gender & Other Impact Gender Other Provide the baseline, targets and metrics to measure the impact Gender Do not confuse "gender dimension" (i.e. integrating sex and gender analysis into the content of the action) with "gender balance" of the research teams (especially in case of the biophotonic themes and CSA in ICT-05) Other Monitor your mailbox and react immediately if contacted Monitor the call/topic website for updates and Q&As/FAQs Home: https://ec.europa.eu/info/funding-tenders/opportunities/portal/screen/home Search for "ICT-03" or "ICT-05" Don't focus only on those parameters which are to be improved (higher speed, higher bandwidth, lower energy consumption, ...) but also on other parameters, e.g., on a module or subsystem level (not on a chip level only)  this is also linked to the "progress beyond the state of the art" For example, if a chip enables much higher operation speed, the cost of related driving electronics is of high relevance and too high driving electronics cost or the need of an RF package could completely counterbalance or undo any possible advantage . Therefore. Comparisons should also be made with SoA at subsystem, module level Promising exploitation potential can be expected if an in-depth comparison between commercially available solutions and a module, subsystem, ... based upon the targeted project results does suggest such potential. However, there is one additional ‘caveat’ in this respect: Comparisons should be made not only with commercial solutions available today, but extrapolate the performance of current commercial solutions to what their expected performance will/might be in about four (or even more) years ahead (“Moore’s law” and similar dependences for optoelectronic chips)