Using FPro SoC with customized hardware cores ECE 448: Lab 4 Using FPro SoC with customized hardware cores

Agenda for today Part 1: Best Student Solution for Midterm Exam Part 2: Introduction to platform organization Part 3 : Hands-on Session on Running Example Design with FPro System Part 4: Lab 4 Exercise 1 Part 5: Lab 4 Assigment

Best Student Solution for Midterm Exam Part 1 Best Student Solution for Midterm Exam ECE 448 – FPGA and ASIC Design with VHDL

Introduction to Platform Organization Part 2 Introduction to Platform Organization ECE 448 – FPGA and ASIC Design with VHDL

Required Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 8: Overview of Embedded SoC Systems Chapter 9: Bare Metal System Software Development Chapter 10: FPro Bus Protocol and MMIO Slot Specification Chapter 14: Debouncing Core and LED-Mux Core Appendix A.4: Tutorial on IP Instantiation Appendix A.5: Short Tutorial on FPro System Development ECE 448 – FPGA and ASIC Design with VHDL

Recommended Materials Book Website http://academic.csuohio.edu/chu_p/rtl/fpga_mcs_vhdl.html Source Codes read_me file: readme_source_code.pdf source file: fpga_mcs_vhdl_src.zip (last updated 11/10/2017) Basys 3 supplement materials read_me file: readme_basys3_adoption.pdf source file: basys3_supplement_src.zip (last updated 12/05/2017) Project files w/ Basys 3 board (in Vivado v2017.2) basys3_vanilla.xpr.zip basys3_sampler.xpr.zip basys3_daisy.xpr.zip ECE 448 – FPGA and ASIC Design with VHDL

Platform Hardware Organization

An Entity Declaration of an MMIO Core

MIMO Core Interface Specification A slot is a 32-word (25-word) memory module. The slot interface is defined as follows: addr (bus to core). A 5-bit address signal used to identify the 32-bit destination I/O register within the core. rd_data (core to bus). A 32-bit signal carrying the read data. wr_data (bus to core). A 32-bit signal carrying the write data. read (bus to core). A 1-bit control signal activated with the read operation. write (bus to core). A 1-bit control signal to enable the register write. cs (bus to core). A 1-bit enable (i.e., “chip select”) signal to select and activate the core.

Platform Software Organization

Data Types in inttypes.h int8_t: signed 8-bit integer uint8_t: unsigned 8-bit integer int16_t: signed 16-bit integer uint16_t: unsigned 16-bit integer int32_t: signed 32-bit integer uint32_t: unsigned 32-bit integer int64_t: signed 64-bit integer uint64_t: unsigned 64-bit integer

Device Drivers: Timer Core (timer_core.h) class TimerCore { public: … void pause(); void go(); void clear(); uint64_t read_tick(); uint64_t read_time(); void sleep(uint64_t us); private: };

Device Drivers: Timer Core (chu_init.h) unsigned long now_us(); unsigned long now_ms(); void sleep_us(unsigned long int t); void sleep_ms(unsigned long int t);

Device Drivers: Timer Core #include "chu_io_map.h" #include "timer_core.h" #include "chu_init.h" TimerCore timer((get_slot_addr(BRIDGE_BASE, S0_SYS_TIMER))); int main(){ timer.clear(); timer.go(); timer.pause(); uint64_t ticks = timer.read_tick(); timer.sleep(1000000); sleep_us(1000000); sleep_ms(1000); }

Device Drivers: Uart Core (uart_core.h) class UartCore { … public: int rx_fifo_empty(); int tx_fifo_full(); void tx_byte(uint8_t byte); int rx_byte(); void disp(char ch); void disp(const char *str); void disp(int n, int base, int len); void disp(int n, int base); void disp(int n); void disp(double f, int digit); void disp(double f); private: };

Device Drivers: Uart Core #include "uart_core.h“ #include "chu_io_map.h" UartCore uart((get_slot_addr(BRIDGE_BASE, S1_UART1))); int main(){ uart.disp("ECE448 FPro \r\n"); uart.disp(5); int n = 10; uart.disp(n); }

Device Drivers: GPI Core (gpio_cores.h) class GpiCore { … public: uint32_t read(); int read(int bit_pos); private: };

Device Drivers: GPI Core #include "gpio_cores.h“ #include "chu_io_map.h" GpiCore Gpi(get_slot_addr(BRIDGE_BASE, S3_SW)); int main(){ uint32_t all_sw = Gpi.read(); int sw_0 = Gpi.read(0); int sw_1 = Gpi.read(1); }

Debouncer Core (gpio_cores.h) class DebounceCore { … public: uint32_t read(); int read(int bit_pos); uint32_t read_db(); int read_db(int bit_pos); private: };

Debouncer Core #include "gpio_cores.h“ #include "chu_io_map.h" DebounceCore debouncer(get_slot_addr(BRIDGE_BASE, S7_BTN)); int main(){ uint32_t all_btns = debouncer.read_db(); int btn_0 = debouncer.read_db(0); int btn_1 = debouncer.read_db(1); }

Device Drivers: SSD Core (sseg_cores.h) class SsegCore { … public: uint8_t h2s(int hex); void write_1ptn(uint8_t pattern, int pos); void write_8ptn(uint8_t *ptn_array); void set_dp(uint8_t pt); private: };

Device Drivers: SSD Core (sseg_cores.h) #include "sseg_core.h“ #include "chu_io_map.h" SsegCore seven_seg_disp(get_slot_addr(BRIDGE_BASE, S8_SSEG)); int main(){ seven_seg_disp.set_dp(0); uint8_t pat_0 = seven_seg_disp.h2s(0); uint8_t pat_1 = seven_seg_disp.h2s(1); uint8_t pat_15 = seven_seg_disp.h2s(15); // display F100 in 7 segment display seven_seg_disp.write_1ptn(pat_0, 0); seven_seg_disp.write_1ptn(pat_0, 1); seven_seg_disp.write_1ptn(pat_1, 2); seven_seg_disp.write_1ptn(pat_15, 3); uint8_t pat_arr[8] = {0}; pat_arr[0] = pat_0; pat_arr[1] = pat_0; pat_arr[2] = pat_1; pat_arr[3] = pat_15; seven_seg_disp.write_8ptn(pat_arr); }

Hands-on Session on Running Example Design with FPro System Part 3 Hands-on Session on Running Example Design with FPro System ECE 448 – FPGA and ASIC Design with VHDL

Part 4 Lab 4 Exercise 1 ECE 448 – FPGA and ASIC Design with VHDL

16-bit Binary Up-Down Counter Design, implement, verify, and test using the FPro SoC on Basys 3 board a 16-bit Binary Up/Down Counter in C/C++ Your code should make use of : Timer core for timing GPI core for reading switches Debouncer core for reading buttons Sseg core to control seven-segment displays UART core to send debug information to host computer.  

Part 5 Lab 4 Assignment ECE 448 – FPGA and ASIC Design with VHDL

The Simon Game using FPro SoC   PRNG  

The PRNG Core   PRNG  

Tasks Write synthesizable VHDL code for the customized PRNG Core. Write testbench to test the PRNG Core. Synthesize your design together with FPro subsystem and all required available VHDL code. Implement your code using the customized Basys 3 XDC file for this project. Check the timing report and make sure there are no timing violations. Generate the bitstream. Write C/C++ code for FPro system to implement the Simon game specification. Generate the .elf file and program the FPGA. Verify experimentally the correct operation of your circuit.

Deliverables VHDL Code for the customized PRNG Core. A simple testbench and functional waveform VHDL Code of the Entire System (including code accompanying the textbook). All systhesis and implementation report files. Entire C/C++ Code used (including code accompanying the textbook). Constraints files for the entire system.