Han Liu Partner: Dongdong Chen Supervisor: Seok-Bum Ko

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Presentation transcript:

Improved Architecture of Logarithmic Converter by Digit-Recurrence with Selection by Rounding Han Liu Partner: Dongdong Chen Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Mar-30

Outline Background Introduction of Algorithm Previous Design Improvements on Architecture Comparison

Background Decimal Floating Point format: Logarithm of V is: V=(-1)S×10E×Significand Logarithm of V is: R=log10(V)=log10(10E)+log10(Significand) Since DFP is not a normalized number, then after normalizing significand to range [0.1, 1), then R is represented in, R=E+k+log10(m) Significand = m × 10k

Introduction of Algorithm (1/2) log10(m) = log10(m∏fj)-∑log10(fj) where lim{m∏fj} → 1, then lim{log10(m∏fj)} → 0 thus log10(m) = 0 - ∑log10(fj) (fj = 1+ej10-j) E[j+1] = E[j] ×(1+ej10-j) L[j+1] = L[j]-log10(1+ej10-j) where E[1] = m, L[1] = 0

Introduction of Algorithm (1/2) E[N+1] ≈ 1 L[N+1] ≈ log10(m) W[j] = 10j(1-E[j]) so E[j] = 1-W[j]10-j W[j+1] = 10(W[j]-ej+ejW[j]10-j) where W[1] = 10(1-m’) m : [0.1, 1) m’ : [0.5, 1)

Previous Design

Improvements on Arch. (1/4)

Improvements on Arch. (2/4)

Improvements on Arch. (3/4)

Improvements on Arch. (4/4)

Comparison TSMC-180 nm ST-90 nm Previous design (32bit) 9.26 ns 5 ns Improved design (64bit) NA 1.1 ns Comparison on critical path

Question Thanks!