Readout At ESS JINR and ESS Collaborative Workshop 5th March 2019 Steven Alcock, Detector Group

Contents Explain the motivations, scope and design concept for ESS readout electronics. Report progress to date. Steven Alcock, Detector Group, 5th March 2019

What Is Readout Electronics? Detectors produce electrical charge in response to neutron events. Charge passes through Front End analog electronics (preamps, shapers). Finally, charge digitised by an Analog to Digital Converter (ADC). ADCs need additional digital electronics to provide: Clocking/timing, Configuration/control, Sample processing. A given instrument may require large numbers of ADCs. Backend digital electronics is required to coordinate the timing, control and data paths between these ADCs and the ICS (Integrated Control System) and DMSC (Data Management and Soft Centre). Steven Alcock, Detector Group, 5th March 2019

Where to Standardise? Commissioning, maintenance and support generally easier if different Instruments use a common readout. Instruments may use different front-end ASICs! Try to standardise at the front end where possible, with a common interface to the ICS and DMSC. Steven Alcock, Detector Group, 5th March 2019

Readout Architecture ICS (timing/slow control) DMSC (science data) Backend Master Internal Routing and Aggregation MFE ICS MFE DMSC MFE MFE MFE MFE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE ADC ADC ADC ADC ADC ADC ADC ADC ADC … … … … … … … … … Detector Channels Steven Alcock, Detector Group, 5th March 2019

In-Kind Collaboration Frontend readout developed between ESS and Instrument partners. Backend readout developed by Science & Technology Facilities Council at Rutherford Appleton and Daresbury Laboratories. Steven Alcock & Harry Walton, Detector Group & STFC, 5th March 2019

Prototyping: Front End Handover ICS (timing/slow control) DMSC (science data) Backend Master MFE Internal Routing and Aggregation ICS MFE DMSC MFE MFE MFE MFE FEA FEA FEA FEA FEA FEA FEA FEA FEA FEE FEE FEE FEE FEE FEE FEE FEE FEE ADC ADC ADC ADC ADC ADC ADC ADC ADC … … … … … … … … … Detector Channels Steven Alcock, Detector Group, 5th March 2019

Prototyping: Front End Handover Current prototyping platform: Xilinx KC705 Commercial board, Kintex 7-Series FPGA Next stage is to move to an ESS custom platform, ultimately interfacing to appropriate ASICs (eg the VMM). Default FPGA is Xilinx Artix 7-series Steven Alcock & Harry Walton, Detector Group & STFC, 5th March 2019

Front End Clock Distribution Tests Harry Walton, STFC, 11th September 2018

Front End Timestamp Distribution Tests Harry Walton, STFC, 11th September 2018

Readout Architecture ICS (timing/slow control) DMSC (science data) Backend Master Internal Routing and Aggregation MFE ICS MFE DMSC MFE MFE MFE MFE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE FEA FEE ADC ADC ADC ADC ADC ADC ADC ADC ADC … … … … … … … … … Detector Channels Steven Alcock, Detector Group, 5th March 2019

Prototyping: Backend Hardware Proposal is to use Xilinx VCU118 Development board for prototyping and deployment due to favourable price and performance. Xilinx Virtex Ultrascale+ FPGA (XCVU9P). 2x 100 GbE for DMSC interface, USB or 1 GbE for ICS slow control interface, FMC+ card for front end interface, FMC card for ICS timing interface. Steven Alcock & Harry Walton, Detector Group & STFC, 5th March 2019

Next Steps Finalise backend interfaces and hardware. Scale up front end ring size. Integrate front end ASICs. Conduct full end-to-end tests. Start instrument integration. Steven Alcock, Detector Group, 5th March 2019

Questions