A Faster Digitizer System for the Hadron Blind Detector in the PHENIX Experiment Cheng-Yi Chi Nevis Lab Physics Dept. Columbia University for the PHENIX experiment N35-6 Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

HBD Team Weizmann Institute of Science Stony Brook University A.Dubey, Z. Fraenkel, A. Kozlov, M. Naglis, I. Ravinovich, D.Sharma, I.Tserruya* Stony Brook University W.Anderson, Z.Citron, J.M.Durham, T.Hemmick, J.Kamin Brookhaven National Lab B.Azmoun, A.Milov, R.Pisani, T.Sakaguchi, A.Sickles, S.Stoll, C.Woody (Physics) J.Harder, P.O’Connor, V.Radeka, B.Yu (Instrumentation Division) Columbia University (Nevis Labs) C-Y. Chi, F.W. Sippach * Project Leader

Triple GEM module with mesh grid Honeycomb panels Mylar entrance window HV panel Pad readout plane Triple GEM module with mesh grid HADRON BLIND DETECTOR Proximity focus Cherenkov counter. Use CsI to convert photon to electron. GEM is used for amplify the electron from CsI. Measure time and charge Installed in 2006 Mesh CsI layer Triple GEM Readout Pads e- Primary ionization g HV N05-1 HBD I.Tserruya N15-295 HBD Gas S.Stoll MP5-3 Gain J.S.Kamin N15-239, GAS B. Azmoun MP4-2 Foil B. Azmoun Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

Charge Preamp with On-Board Cable Driver (IO1195-1-REVA) Preamp (BNL IO-1195) 2304 channels total 19 mm 15 mm Features: +/- 5V power supply. 165 mW power dissipation. Bipolar operation (Q_input = +/- ) Differential outputs for driving 100 ohm twisted pair cable. Large output voltage swing -- +/- 1.5V (cable terminated at both ends) (+/- 3V at driver output) Low noise: Q_noise = 345e (C_external = 5pF, shaping = .25us) (Cf = 1pF, Rf = 1meg) Size = 15mm x 19mm Preamp output (internal) will operate +/- 2.5V to handle large pile-up. Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

Use 2MM Hard Metric cable to move signals between preamp/FEM 2mm HM connector has 5 pins per row and 2mm spacing between pins and rows There are two types of cable configuration: *100 ohms parallel shielded cable 50 ohms coaxial cable Signal arrangement S- S+ G S- S+ MERITEC Our choice is This gives us signal density 2mm x 10mm for every 2 signals. Same type of cables will be used for L1 trigger data. Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

FEM receiver + ADC Preamp Cable driver Differential Receiver ADC FPGA TI ADS5272 Based on AD8138 receiver Unity gain 8 CHANNEL 65 MHz 12 bits ADC (80 TQFP) The +/- input can swing from 1V to 2V, Vcm=1.5V + side 2V, - side 1V -> highest count - side 2V, + side 1V -> lowest count Our +/- input will swing from 1.5 to 2V/ 1.5 to 1V we will only get 11 bits out of 12 bits 16fc will be roughly sitting at 200 count We will run the ADC at 6X beam crossing clock 6X9.4 MHz = 56.4 MHz or ~17.7ns per samples ADC data are serialized LVDS at 12*56.4 MHz= 678 MHz Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

HBD ADC board 48 channels per board 6U X160 mm size We use ALTERA STRATIX II 60 FPGA to receive the 6 ADC’s data It has 8 SERDES blocks. ALTERA provides de-serializer Mega function block. 6XADC clock  SERDES clock  data de-serialized as 6 bit 120 MHZ  Regroup to 12 bits at 60 MHz , 45 degree phase adjustment step. Timing Margin  270 degree. The FPGA also provides L1 delay (up to 240 samples) 8 events buffer ADC setting download Offline slow readback 7 threshold levels for L1 trigger primitives per channel. ALTERA FPGA ADC Differential receiver 48 channels per board 6U X160 mm size Signals from Preamp Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

FEM Crate Block Diagram FEM: Digitize the detector pulse Clock Fanout -> distribut the ADC + system clocks XMIT: send the digitize data to DAQ Pulse: send the test pulse to the preamp Clock Master: Interface with PHENIX timing system for L1, clock etc. DCM: PHENIX Data Collection Module FEM CRATE 60MHz ADC clock 20MHz system clock Token passing dataway 60MW/sec Clock fanout FEM (ADC) FEM (ADC) XMIT Pulser 80MW/sec Optical link Clock Master Preamp GTM + Ethernet DCM Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

16MV test pulse on all the channels on FEM number 2 The test is done by moving test jigs cables (6 outputs) 8 times. 60Mhz noise kicks back from ADC Preamp output Output of FEM receiver 10mv, 100ns per division Digital sum 20mv/division Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

Sigma on the baseline ADC distribution ADC test result -2 Average over 40 events Preamp + ADC system performance ADC Sample # Preamp on Preamp off Sigma on the baseline ADC distribution for 192 channel ADC distribution for sample 15 TEST Pulse Injection at preamp input Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

< problem with the low drop regulators> ADC test result -3 ADC The result after doing Pulse (n+2) – Pulse (n) Sample Number ADC ADC Distribution Sample Number 100 events histogram from test pulse injection. < problem with the low drop regulators> ADC Distribution Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

CONCLUSION We have ~2300 channel installed. The electronics has been installed and run successfully in 2007 run. We have ~2300 channel installed. The FEM board power consumption is about 20W for 48 channel. The whole system fit into 4 crates, including the enough space of adding L1 trigger boards. We read out 12 samples of ADC data per channel. The channel has ADC (peak – baseline) < threshold (channel) get dropped in the data acquisition system. Both TI and Analog Device now have multiple channels 14 bits ADC. We will develop a new system for 14 bits application with slightly higher packing density. Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi

Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi