for the trigger subsystem working group: A.Nappi, May 14,2004 for the trigger subsystem working group: P.Amaudruz, N.Cartiglia, E.Imbergamo, S.Kettell, A.Nappi, T.Numao, G.Redlinger, R.D.Schamberger,

Boundary conditions 80% of the bunchlets (25MHz) have at least 1 hit with E>5MeV in the preradiator (Ermanno’s study) “Singles”  20MHz Aim: tolerate a maximum 5% inefficiency on top of the efficiency due to background separation cuts Rate limitations not yet well known Preradiator chamber readout can take a rate of L1 triggers, with 10s latency, in excess of 100kHz Uncertainties related to: wire hit rate, readout formats, bandwidth of various interconnection links Unified scintillator readout by WFD: Rate limits to be assessed

Prerad data rates (P. Amaudruz) more details Readout Card Chamber Collector Module Collector Anode TDC FPGA FPGA 24ch. FPGA Wire hit Rate 30KHz B D A 96ch. 8 x 96ch. 90Mbits/s >200Mbits/s LV1 100KHz 8 x 8 x 96ch. 200Mbits/s Multiplicity For LV2 LV2 ADC FPGA C 96ch. Data rates (Mb/s) for 100kHz trigger, 100kHz WHR: A : 13 ; B : 23 ; C :15(42) ; D : 152(260) 12 bit “charge” output (full digitizations) Strip hit Rate 150KHz Cathode

Design guidelines Assume, as a work hypothesis, “traditional” 3 level structure à la ATLAS Level 1 Input: subdetector data through data paths parallel to standard readout (trigger primitives) Output Time stamp of selected events Regions of interest of selected events Level 2 Based on (subset of?) readout data before event building Output: decision to pass event to event building Level 3 After event building

Traditional (3 level) scheme Special data path Readout system Readout system First Level ? ? . . . . . . . . Buffer cards Second level processor Buffer cards Second level processor Switch . . . . Event buiders Event buiders

Schematics of the data flow Level 1 Level 2 Level 3 Front end pipelines Output buffers Event building Front end pipelines Output buffers Permanent storage . . . . . Front end pipelines Output buffers

Simulation results Rate/efficiency estimates (George)

More about George’s results: plots     e  + – 0 30

Some data from Ermanno: Energy distributions ( 2 cluster ev.) E in MeV 0 Bunchlet

Handles for further rejection Work in progress by Ermanno and George Reject tracks from inside PR and/or upstream region Energy cuts Selective use of veto counters with individually optimized windows Kinematic correlations?

Open issues We do not have yet a fully satisfactory set of conditions that achieve the target efficiencies and rates Not clear at the moment whether level 1 can achieve a rejection sufficiently interesting to be used in the front end modules to control the transfer from input pipelines to readout buffers This creates interest in an option where level 1 is abolished altogether. There is an intermediate option where level 1 is not used by the front end modules, but is still interesting as a first trigger level using preelaborated information from the front end

Two level scheme George’s proposal

Triggerless readout ? CKM vs KOPIO comparison by S.Kettel CKM triggerless scheme send 250s “macroslices” from each frontend to each processor 400 sources*4000 slices L1 runs in software Identifies events based on the time of each K+ Reduction factors: L1: 30MHz,50GB  4GB Higher levels:  100MB/s Estimated cost: ~$2M

Status of the design Only a provisional work hypothesis on a general architecture exists Even that is subject to the uncertainty on the number of levels Indications for basing LV1 design on the assumption of a ~10s latency No work has gone into developing concrete implementation proposal Guidelines that get some consensus: try to build all trigger conditions based on digitized time and amplitude information a parallel data processing path for the trigger may be useful not only for L1, but also to provide redundancy to the scintillator readout trigger design may be simplified if signals are timed to have the same phase w.r.t the clock

Plan of attack MC: List of setup cuts LV1: High level design of PR+CAL level1 scintillator logic cluster conditions Boolean logic LV2: Develop realistic proposal and understand possible performance MC: List of setup cuts set of realistic condi- tions to achieve 95% efficiency with minimum rate Point of decision: How many levels What is done in each level Parallel processing path for scintillator signals Design at the level of logical boxes, data formats, definition of communication paths Preliminary cost estimates

Manpower For this to become a schedule with the baseline review as a deadline, a crash effort is needed People presently involved E.Imbergamo, G.Redlinger, S.Kettell, A.Nappi @ variable fractions of their time Two more physicists + one electronic engineer working at a large fraction of their time on this project would be needed

Conclusions Trigger work still in its infancy Problem appears more arduous than anticipated Contribution of events not from fiducial region Veto losses Two main lines of attack being pursued in parallel Improve level 1 rejection to a level such that front end systems can cope with Investigate possibility of triggerless front end Need to develop concrete implementation schemes Lots of room for new ideas and contributions

Reserve slides

Performance of TDC chip (P.A.Amaudruz) Trigger rate that saturates the TDC-FPGA link (left scale) Average TDC buffer level (right scale)