3D sensors: status and plans for the ACTIVE project Gian-Franco Dalla Betta University of Trento and INFN Via Sommarive, 14 I-38123 Povo di Trento (TN) e-mail: gianfranco.dallabetta@unitn.it

Outline Status: the IBL campaign Latest results and on-going tests New requirements for phase 2 upgrades Possible approaches and related problems Proposed activity in ACTIVE Cost estimate

3D sensor development for ATLAS IBL Process and design aspects Fully double sided process No support wafer (substrate bias from the back side) Empty columns, with 11 um diameter and 230 um thickness Slim edge (200 um for IBL, but also tested down to 75 um for AFP) Temporary metal for I-V tests Main results Tested with FE-I3, FE-I4 and CMS ROCs (laboratory and beam test) Qualified for ATLAS IBL: >98% efficiency for 15º tracks at 160 V after 5x1015 neq/cm2 IBL production at FBK with ~50% yield Deep understanding of sensor behavior C. Da Via, et al., NIMA 694 (2012) 321 G.F. Dalla Betta, et al., JINST 7 (2012) C10006

Yield on Selected Wafers (%) Critical aspects G. Giacomini, et al., IEEE TNS 60(3) (2013) 2357 Relatively low intrinsic breakdown voltage (p-spray related, well understood) Might be an issue for post irradiation performance High sensitivity to process defect (a single defect kills an entire sensor) High yield variability Batch Tested Wafers Selected Wafers Total Sensors Number of Good Sensors Yield on Selected Wafers (%) 3D ATLAS 10 20 12 96 58 60% 3D ATLAS 11 11 4 32 14 44% 3D ATLAS 12 16 13 104 63 61% 3D ATLAS 13 15 47%

After IBL: modified 3D process M. Povoli et al., IEEE NSS 2012 A modified (simpler) process has been defined and tested The first batch had major fabrication problems (high bowing, very low yield) Promising indications from 3D diodes: Significant improvement in intrinsic breakdown voltage, as expected from simulations New slim edge (50um) proved to work M. Povoli, et al., IWORID 2013

Present status at FBK FBK production line upgrade from 4” to 6” wafers completed Activity restarted in Spring 2013 with internal test batches 6” allows for higher production volumes (>2x area on wafer, e.g., can host more than 30 FE-I4 sensors)  lower sensor cost DRIE upgrade with a thin ceramic edge protection will simplify the process and increase the mechanical yield BUT Need to learn how to process thin wafers on 6” (what is the limit ? Wafer procurement below 275 um is difficult) Double-sided 3D process might not be the best option (or not at all feasible) for thin sensors  need to explore possible alternatives (including epitaxial wafers).

Implications for future pixels Smaller pixel size in future ROCs (e.g., 150 x 25 mm2) requires a thinner sensor (or at least the collecting charge thickness) to take advantage of the high-pixel spatial resolution. Smaller inter-electrode distance for radiation hardness Both lead to higher column density and bump density Narrower electrodes desirable for higher geometrical efficiency and lower capacitance This also calls for thinner substrates given a constant column aspect ratio with DRIE Thinner substrates also help with electrode (at least partial) filling with poly-Si to obtain some efficiency (also using oxygen-free doping gas)

Possible approaches (1): Double-Sided with Local Thinning Maintain the double-sided approach on 6” wafers of thickness compatible with the equipment (275 um) Local thinning of sensor active areas with DRIE or TMAH Advantages: exploit the experience with double-sided process, sensor bias from the back-side, no support wafer (bonding and removal), Disadvantages: mechanical fragility, lithography on etched regions, active edge not feasible

Possible approaches (2): Single-Sided with Support Wafer Switch to a single-sided approach on 6” wafers of requested thickness + support wafer OR epitaxial wafers SiO2 Sensor wafer Epi layer P++ Substrate Support wafer Advantages: mechanical robustness, active edge feasible Disadvantages: support wafer (bonding and removal), bias from the front-side (layout ?). Post processing for back-side bias ? Easier with epi …

Possible approaches (3): Double-Sided with Support Wafer Merge a double-sided approach on 6” wafers of requested thickness + support wafer + local thinning SiO2 Sensor wafer SiO2 Sensor wafer Support wafer Combines advantages of double-sided and single-sided approaches … feasibility to be proved, but it could be the best option (with all steps at FBK …).

ACTIVE WP1 : proposed activity GOALS Fabrication of new 3D pixel sensors on 6” wafers with thinner active region Technology and design to be optimized and qualified for extreme radiation hardness (2x1016 neq/cm2) Pixel designs compatible with present (for testing) and future (65nm) FE chips of ATLAS and CMS STRATEGY Preliminary technological tests (6 months) to check the feasibility of the most critical steps for the different process approaches Two sensor batches with the technology of choice.

SPECIFIC OBJECTIVES Smaller pixels with narrower electrodes (related to thickness) Reduced inter- electrode distance for radiation hardness Higher breakdown voltage Improved electrode efficiency Very slim (or active) edges Sensor thickness to be optimized (depending on signal/threshold) - case 1 ~ 150 mm: still feasible with “passive” sensor - case 2 < 100 mm: calls for charge multiplication …

Charge multiplication in thin 3D M. Povoli et al., submitted to NIMA 70 mm thickness

Expected performance M. Povoli et al., submitted to NIMA

Fabrication cost estimate (tbc) Item Preliminary tests 1st batch 2nd batch Wafer procurement (SOI, wafer bonding or epi) 10 kEuro 5 Processing at FBK 15 30 60 Support wafer removal (*) 10 kEuro Post processing for back-side bias (*) TOTAL 35 55 85 kEuro Fabrication costs for preliminary tests and 2 batches ~175 kEuro (*) If all processing at FBK, savings possible.