Electronics, Trigger and DAQ for SuperB: summary of the workshop. Dominique Breton, Umberto Marconi D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Overall system architecture proposal D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Summary of the ETD parallel sessions (1) We had encouraging presentations about the high speed links: Main difficulty is to get fixed link latency and jitter There already is a solution for a fully FPGA-based link => OK for the off-detector links Jitter measurements are at the level of 20ps rms. R&D work has to start on the detector side to find a solution for the radiation area First commercial components have been chosen => we need to validate them. Alberto Aloisio (INFN Napoli) has been given the charge of managing these activities. He will soon propose us a roadmap for R&D. Based on the experience acquired on the AGATA experiment, a tentative proposal for the design of the ROM has been shown. Padova and Bologna are interested in this design. D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Summary of the ETD parallel sessions (2) We need a field bus for the ECS link to the detector The SPECS bus, designed for LHCb, has been presented. It has the advantage of being easily adaptable for SuperB Time schedule for delivery would be very short It would come with all the necessary software We had a presentation from engineers of the CAEN company They are of course interested as usual in the field of all types of power supplies But they also described us their different products in the field of high speed digitizers and TDCs They would be interested in collaborating in some of our designs Could they take care of producing the SPECS system if chosen ? D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Architecture of the ETD system The two documents we already released (requirements and architecture) will be our base for the TDR. Yesterday, there was a global agreement on the overall system architecture with our colleagues: There doesn’t seem to be difficulties for the subsystems to fit with it. A few points have been discussed and an updated version of the architecture document will be released soon. We need to distribute the responsibilities over the different elements of the ETD system for the TDR writing: OK for the fast links. Options for the ROM design. There is a proposal for the ECS field bus from LAL. LAL could also take care of the FTCS system. Activities linked to L1 trigger are still uncovered. D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Highlights on the subsystems: SVT SVT made an interesting proposal for a compromise solution in order to: Not to have to put the optical link drivers in the high radiation area Being able to keep all readout solutions open (L1 buffers on detector or data driven readout up to 3Gbits/s) D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Highlights on the subsystems: DCH Work has started at LNF on the DCH electronics. DCH FEE is where the first SEUs were seen in BABAR (1 SEU/ROIB/hour). BABAR’s FEE architecture is the baseline for the new design. Cluster counting is being studied It looks very interesting for dE/dX measurements but it could be difficult to manage at the level of 10kChannels (power dissipation and system calibration) “Local derivative” method Fast analog memories (TARGET chip from Hawaii) are being looked at to get both the time and shape information from the signal. D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Highlights on the subsystems: PID The PID group went farther in the definition of its FEE architecture. For the Barrel, because of the “relaxed” time precision requirements (100ps), a multi-channel TDC based solution could become the baseline. An amplitude measurement could however be helpful not only for debugging and commissioning, but also to help improving the time resolution or the hit position (depending on the detector design choice) => an analog ASIC would have to be designed then. But R&D goes on with TARGET analog memories. For the TOF, fast analog memories have to be used to reach the ultimate performance needed. In both cases, boards from Hawaii are already being tested and boards from Orsay/Saclay will soon be tested on the SLAC cosmic telescope (with MAPMTs and MCPPMTs). Clock distribution for TOF will be a dedicated study, apart from the overall architecture, because the jitter requirement is at the level of a few ps D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Highlights on the subsystems: EMC Design a new ADB board compatible with the old mechanical structure Use two gains (x1 & x32) and a new ADC with more bits (12bits instead of 10bits) Lower power consumption using new FPGAs, new ADC and LVDS logics instead of ECL. Design a new IOB compatible with the new FCTS and ECS system Design a preamplifier for EMC FWD with x1 and x32 outputs compatible with Barrel preamp (light detector will be either APD or PIN diode). Trigger primitives have not to be forgotten. D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

Highlights on the subsystems: IFR IFR decided to put the very front-end part of its FEE directly on the detector (because it was finally rejected the idea of carrying scintillation light out of the iron on clear optical fiber due to excessive attenuation) )  this part of the FEE will have to be power-optimized and characterized for radiation tolerance. Problems with finding a multi-channel TDC working @ 56MHz … and also to deal with the trigger time window with available circuits. Timing readout for Barrel, binary readout for endcaps. Study of data rates look OK. D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009

D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009 Conclusion We really moved forward during the last months. We now have a system architecture in hand. We have the written basis for the TDR writing. Subsystems started thinking of the integration of their FEE in the whole system. We started getting better estimations of the data rates and number of links from sub-detectors (please go on). We had fruitful discussions about how going forward. We really need a map of the estimated radiation level on the detector If ever the integrated dose would pass above ~50kRads somewhere (except of course in the SVT), we would be in big trouble We started distributing the work to different teams. Others expressed their interest in different items. Anyway, we still miss manpower, especially for what concerns the L1 trigger. D.Breton, U.Marconi, Perugia SuperB Workshop – June 16th 2009