ECE 352 Digital System Fundamentals One-Hot State Machine Design In this presentation, we will look at a different way of encoding the states in an FSM.

Min FF Example: Ring Counter Could use a minimum flip-flop technique… Use an arithmetic order for state assignment A decoder takes in current state and produces the circuit outputs Let’s look at an example involving the design of a ring counter. This is a special form of counter where the output bits are all 0 except for a single bit that is 1, and the position of the 1 rotates through the output word as the circuit counts. Since this counter has four states, a minimum flip-flop design requires two flip-flops. We assign the 2-bit state values in arithmetic order so state S0 has value 0, state S1 has value 1, and so on. Then we use a decoder to translate the current state into the 4-bit ring count output. Note that the reset signal forces the FSM to state S0 by clearing both flip-flops. Two flip-flops Four states (00, 01, 10, 11) Reset into state 00

One-Hot State Assignment Alternative to minimum FF assignment If m states, use m flip-flops The current state is defined by the flip-flop that contains a 1 (all others MUST contain 0) i.e., “one” of the flip-flop outputs is “hot” (a “1”) This method is also called “one flip-flop per state” Conceptually, the “1” is a token passed from the current state to the next state In reality, a FF’s input logic will produce a 1 if and only if that FF is the next state As an alternative to using the minimum number of flip-flops based on the number of states, we can instead use one flip-flop to represent each state. Each flip-flop holds a value indicating whether or not the current state is represented by that flip-flop. The flip-flop for the current state holds a 1, the others all hold 0s. The flip-flop holding a 1 is said to be “hot”, and since only one flip-flop can be “hot” in this design method, it is called “one-hot”. In a one-hot FSM, a transition between one state and another is conceptually like the flip-flop for the current state passing a token (the 1) to the flip-flop that corresponds to the next state. There’s only ever a single flip-flop storing a 1 because the circuit can only be in a single state at a given time. This also means that the D input to a flip-flop will be 1 ONLY when the next state corresponds to that flip-flop.

Create Hardware From Diagram Does not require a state table! One flip-flop per state Create an AND gate per incoming transition and OR these together to make FF input logic Moore outputs: OR together outputs of FFs that represent states where the output is 1 Mealy: create an AND gate for each transition where the output is 1, and OR these together “What are all the ways this can be the next state?” So why should we bother learning another design method that requires more flip-flops? The answer is that it results in very simple next-state and output logic. In practice, we often use the one-hot method to design very fast FSMs, since the more simple logic has less delay at the expense of needing more flip-flops. But it is also quicker to design, easier to modify if the state diagram is changed… and very often easier to fix if we’ve made a mistake in our design. In fact, we don’t even need a state table to design the logic. First, we place a flip-flop for each state. Then the next state logic for each flip-flop is added by ORing together a set of AND gates, one AND gate per transition pointing towards the state represented by that flip-flop. This input logic answers the question: “What are all the ways that this can be the next state?” Next we design the output logic. For a Moore machine, we simply OR together all the outputs of the flip-flops representing states where the output should be 1. For a Mealy machine, we create an AND gate for each transition where the output is 1, and OR those together. Thus, the output logic answers the question: “What are all the ways this output can be 1”? “What are all the ways this output can be 1?”

One-Hot Example: Ring Counter Each state gets a FF State vector is the output Let’s look at our ring counter example again. The ring counter has four states, so we use four flip-flops. All state transitions are unconditional, so we know that the only way S1 is the next state is if S0 is the current state. This means we connect the input of flip-flop S1 to the output of flip-flop S0. The other state transitions are similar. The state vector is used as the output, so there is no additional output logic required. Remember that the state is the set of values stored in ALL of the flip-flops. In this case, the flip-flop indices indicate their position in the state vector—flip-flop S0 holds bit 0 of the state, flip-flop S2 holds bit 2 of the state, etc. So, if we’re in state S0, the state vector is 0001 because flip-flop S0 holds a 1 and the other flip-flops hold 0s.   Four flip-flops Four states (0001, 0010, 0100, 1000) Reset into state 0001 (S0)

One-Hot Reset State Remember, exactly one FF must contain a 1 at any moment Which state is the current state? The one that has a flip-flop with an output equal to 1 Which state is the next state? The one that has a flip-flop with an input equal to 1 On a circuit reset, we need to load 1 into FF that represents the reset state, and 0 into the others Use PRESET (SET) (“on reset, become 1”) for that FF Use CLEAR (RESET) (“on reset, become 0”) for others A one-hot FSM must ALWAYS have exactly one flip-flop that is storing a 1. No more, no less. If none of them hold a 1, that would imply that the circuit isn’t in any state. If more than one flip-flop holds a 1, then it would imply the circuit is in multiple states. Neither of these cases make sense. By the way, these are good things to check for when debugging a one-hot FSM! When we use the global circuit reset to force the FSM into its initial state, we need to ensure that one and only one flip-flop is storing a 1. All other flip-flops must be storing a 0. This means we connect the global reset to the asynchronous preset input on the flip-flop that represents the initial state, and to the asynchronous clear input on all other flip-flops. You should already be familiar with how preset and clear work. If not, now would be a good time to review that.

One-Hot Example: Ring Counter Each state gets a FF State vector is the output This FF represents the reset state S0 For our ring counter example, we used flip-flops with active-low asynchronous preset and clear inputs. So we pass the active-high global reset through an inverter. We connect the inverted reset input to the asynchronous preset input of the flip-flop for S0 because that’s the one that has the reset arrow in the state diagram. We also disable the unused asynchronous clear by connecting it to 1 – remember, it’s active-low. Then we connect the inverted reset input to the asynchronous clear input of all the other flip-flops, and disable their unused asynchronous preset inputs. When the global RST signal goes to 1, the PRN input of flip-flop S0 will be 0, and the CLRN inputs of the other flip-flops will be 0, so we will enter the state where S0 holds a 1 and the other flip-flops hold 0s, which is, in fact, state S0. Four flip-flops Four states (0001, 0010, 0100, 1000) Reset into state 0001 (S0)

One-Hot Terminology & Naming Since we use one flip-flop per state, we may use the words “state” and “flip-flop” interchangeably If we say the current state is S0, remember the “current state” is actually the complete state vector (all FF outputs, not just FF S0’s output) On the previous slide, the state vector for each state is that state’s output (e.g., state S0 is actually state 0001) This means there are a lot of “unused” states! For state S0 we created a flip-flop named S0 We might name its output S0 (same as the FF) or Q0 We might name its input D0, S0NEXT, etc. Its input and output cannot both be called S0… In the one-hot method, flip-flops and states have a one-to-one correspondence, so we often use those terms interchangeably. However, it is important to recognize that they are not actually the same thing. Although we may say we are in state S0, the state is more than just the contents of flip-flop S0. The actual state vector for an FSM includes ALL its flip-flops. This means that a one-hot FSM actually has a lot of unused states! These unused states include any state where the state vector has more than one 1 in it, plus the state where all bits are 0. In other words, all the illegal state vectors for a one-hot FSM. In the previous example, we named the flip-flops the same as the states they represented. So, the flip-flop representing state S0 was also named S0. Using consistent naming makes it easy to tell when you’re in a state – when the flip-flop with the same name holds a 1. We generally name the flip-flops the same as the states they represent, but there are a few different naming conventions for the flip-flop inputs and outputs. The main things to remember are that the name of a signal should make it easy to know which flip-flop it corresponds to, and we CANNOT name a flip-flop’s input exactly the same as its output because that would imply that they are electrically connected! Most often, we’ll name flip-flops and their outputs the same as their state, and use one of the two ways shown here to name the inputs.

Design Tradeoffs Design Simplicity Circuit Quality Usually less work to create, less work to debug, less work to add a new state because we handle each state separately Circuit Quality The design will require more flip-flops than a “minimum flip-flop” implementation May actually reduce combinational logic area If flip-flop input equations and circuit output equations are simpler as a result… But this is not guaranteed! This means a one-hot design may or may not require more area/delay/power/energy… Using a one-hot design instead of a minimum flip-flop design is a trade-off. The main attraction for us is simplicity. It results in a circuit that is simpler to design, debug, and modify, since the logic for each flip-flop input and each output is determined independently. If you need to change a state transition, you only need to make a simple change to the next-state logic on at most two flip-flops – removing some logic from the state the transition used to point to, and inserting logic for the state the transition now points to. By comparison, changing a single transition in a minimum flip-flop design may force you to redesign the next state logic for every flip-flop because it changes the K-maps for each bit of the next-state logic. On the other hand, the one-hot method uses more flip-flops… but it may actually result in an overall smaller circuit since the combinational logic may be much simpler, requiring fewer gates. But this depends on the specific implementation; the one-hot design may also end up being larger. The fact is that there just isn’t an obvious answer for which method is better – it depends on the specifics of the state machine, and what factors determine what “better” means for that specific case.

Example One-Hot State Machine Pattern recognizer that detects the bit sequences 101 and 11 Overlapping sequences should be detected Design as a Moore machine Implement the state machine using one-hot encoding Let’s look at a design example for a pattern recognizer that detects the sequences 101 and 11, including overlapping patterns. We want to implement the behavior with a Moore machine, implemented using the one-hot methodology. The state diagram for the pattern recognizer is given here – in a real design you’d start by developing the state diagram based on the specification.

Example One-Hot State Machine Create a flip-flop for each state The FSM has five states, so we place five flip-flops, one per state. Notice that each flip-flop and its output has the name of its state, and the inputs all start with the letter D. As we showed, this is one of the common ways to name the signals in a one-hot FSM circuit.

Example One-Hot State Machine Create a flip-flop for each state Implement reset Reset state Other states To implement the reset behavior shown in the state diagram, we connect the reset signal to the preset input on flip-flop Nada, and the clear inputs on all the other flip-flops. We also disable all of the unused asynchronous inputs.

Example One-Hot State Machine Create FF input and circuit output equations DNada = Nada· A + S10· A = (Nada + S10)· A D1 = Nada·A D10 = S1· A + S11· A + S101· A = (S1 + S11 + S101)· A D101 = S10·A Notice that the asynchronous reset is NOT an input to the DNada equation! The reset behavior is handled by the asynchronous clear/preset inputs Then we create the next state and output logic. State Nada will be the next state when we are in state Nada and input A is 0, or when we are in state “10” and input A is 0. Note that we do NOT include the reset signal in the next-state equation for the Nada state. We already used the asynchronous flip-flop inputs to implement that behavior, which will override whatever value appears on the flip-flop’s D input. State “1” will be the next state only when we are in state Nada and input A is 1. State “10” will be the next state when we are in state “1” and A is 0, or when we are in state “11” and A is 0, or when we are in state “101” and A is 0. State “101” will be the next state only when we are in state “10” and input A is 1. State “11” will be the next state when we are in state “1” and A is 1, or when we are in state “11” and A is 1, or when we are in state “101” and A is 1. The output Y is 1 whenever we are in state “11” or in state “101”. Finally, we can use Boolean algebra to simplify the equations before we implement the logic. D11 = S1·A + S11·A + S101·A = (S1 + S11 + S101)·A Y = S11 + S101 Can use Boolean algebra to simplify…

Example One-Hot State Machine The completed circuit…. reusing OR gate Here is the final circuit diagram. Note that we were able to reuse one of the OR gates, since that logic term was present in two of the equations on the previous slide.

one of these has to be a 1 because it always has to be in some state… Mealy One-Hot one of these has to be a 1 because it always has to be in some state… DNada = Nada· A + S10· A = (Nada + S10)· A D1 = Nada·A + S1·A + S10·A = (Nada + S1 + S10)·A = A D10 = S1· A Now let’s look at another implementation of the same pattern recognizer, but this time using a Mealy machine. We know that there will be three flip-flops, one for each state. The next state logic for flip-flop Nada is based on the two transitions into state Nada in the state diagram. The next state logic for flip-flop “1” has three incoming transitions, and since the machine must always be in a state, we can use that to simply the logic. You can also see by looking at the diagram that all transitions where input A is 1, point to state “1”. There is only one transition into state “10”, so only one term in its next state equation. Finally, the output is 1 only in state “1” or in state “10” if input A is 1.   Y = S1·A + S10·A = (S1 + S10)·A

Mealy One-Hot DNada = (Nada + S10)· A D1 = A D10 = S1· A Y = (S1 + S10)·A We can then implement the logic functions, add the flip-flops with the required reset connections, and complete the design. Pause here a moment to compare the circuit to the equations above and to the state diagram.

Optimizing One-Hot FSMs The logic equations from the direct translation may not be as simplified as they could be Optimization may not be critical; we already decided to use more flip-flops than the minimum Design simplicity is a major motivating factor! Some simplifications are straightforward, and can save time when drawing the schematic e.g., the factorization in the Moore example The downside is that changes may be less straightforward when debugging or modifying the FSM In this class, you do not have to simplify one-hot equations (it will be easier to debug!) You saw that the logic expressions obtained directly from the state diagram could often be simplified algebraically. However, the main motivation for using the one-hot design method is simplicity of design along with ease of debugging. As a general rule, you should only do algebraic simplification when it results in a circuit that is easier for you to implement. In this class, we will not require you to optimize the next-state and output logic. This is to help you keep your circuits as easy to possible to debug when they don’t work right, and easier to modify if you discover an error in your state diagram.

ECE 352 Digital System Fundamentals One-Hot State Machine Design This concludes our video on one-hot FSM design.