Microprocessor Architecture

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Presentation transcript:

Microprocessor Architecture The MPU communicates with Memory and I/O using the System Bus Address bus Unidirectional Memory and I/O Addresses Data bus Bidirectional Transfers Binary Data and Instructions Control lines Read and Write timing signals

Microprocessor-Based System

System on a Chip Example Hand Held PC

Microprocessor Data Cache Control Arithmetic Unit & Logic Unit Bus Memory Bus Control Unit Arithmetic & Logic Unit RAM Bus Interface Unit I/O Instruction Decoder Registers System Bus Floating Point Unit Instruction Cache Registers

Bus Interface Unit Receives instructions & data from main memory Instructions are then sent to the instruction cache, data to the data cache Also receives the processed data and sends it to the main memory

Instruction Decoder This unit receives the programming instructions and decodes them into a form that is understandable by the processing units, i.e. the ALU or FPU Then, it passes on the decoded instruction to the ALU or FPU

Data Cache Arithmetic & Logic Unit Bus Interface Unit Instruction Memory Bus Arithmetic & Logic Unit RAM Bus Interface Unit I/O Instruction Decoder Registers System Bus Floating Point Unit Instruction Cache Registers

Arithmetic & Logic Unit (ALU) It performs whole-number math calculations (subtract, multiply, divide, etc.), comparisons (<, >, etc.) and logical operations (NOT, OR, AND, etc.) The new breed of popular microprocessors have not one but two almost identical ALU’s that can do calculations simultaneously, doubling the capability

Floating-Point Unit (FPU) Also known as the “Numeric Unit” It performs calculations that involve numbers represented in the scientific notation (floating-point numbers). This notation can represent extremely small and extremely large numbers in a compact form Floating-point calculations are required for doing graphics, engineering and scientific work The ALU can do these calculations as well, but will do them very slowly

registrar – register – resistor Both ALU & FPU have a very small amount of super-fast private memory placed right next to them for their exclusive use. These are called registers The ALU & FPU store intermediate and final results from their calculations in these registers Processed data goes back to the data cache and then to main memory from these registers

Control Unit The brain of the uP Manages the whole uP Tasks include – - fetching instructions & data, - storing data, - managing input/output devices

Let’s talk about the language of a uP

Machine-level Execution Machine instruction: A bundle of binary bits with certain formats Only asks for simple operations Assembly: textual notations of machine program Example: c = a + b; Machine execution: r1 ← mem(a) r2 ← mem(b) r3 ← ADD r1, r2 mem(c) ← r3

Machine-Level Execution memory I/O address CPU Load Stack Data Store Instruction Fetch inst

Software Machine Language Binary Instructions Difficult to decipher and write Error-prone All programs converted into machine language for execution Instruction Hex Mnemonic Description Processor 10000000 80 ADD B Add reg B to Acc Intel 8085 00101000 28 ADD A, R0 Add Reg R0 to Acc Intel 8051 00011011 1B ABA Add Acc A and B Motorola 6811

Software Assembly Language Machine instructions represented in mnemonics One-to-one correspondence Efficient execution and use of memory Machine-specific

Software High-Level Languages BASIC, C, and C++ Written in statements of spoken languages Machine independent Easy to write and troubleshoot Larger memory and less efficient execution

Major Instruction Types Arithmetic and logic: Add, subtract, multiply, divide; and, or, not, xor Data movement: transfer data between registers and/or memories Control: Branches and jumps

Instruction Set Set of machine instructions that a uP recognizes & can execute – the only language uP knows An instruction set includes low-level, a single step-at-a-time instructions, such as add, subtract, multiply, and divide Each uP family has its unique instruction set  bigger instruction-sets more complex chips (higher costs, reduced efficiency)  but shorter programs