Advanced Computer Architecture Lecture 11 DMA controller FSM design Specific example Lillevik 437s06-l11 University of Portland School of Engineering

Hard drive DMA Requirements Initialization commands Project 5 Requirements Operation: Input, or read disk, or read file HD buffer: represent with a ROM Initialization commands Port 1: start address Port 2: word count Port 4: start Design contains 5 sections Lillevik 437s06-l11 University of Portland School of Engineering

HD system schematic Lillevik 437s06-l11 University of Portland School of Engineering

DMA hardware view n words adr X adr X+(n-1) Memory I/O device buffer System bus adr 0 adr (n-1) Lillevik 437s06-l11 University of Portland School of Engineering

DMA controller block diagram one section Word Count Data Buffer Memory Address Control D A C Xcvr Port1 Port2 BAclr BAinc WCdec MAinc Zero Ben Lillevik 437s06-l11 University of Portland School of Engineering

HD DMA schematic Lillevik 437s06-l11 University of Portland School of Engineering

FSM requirements Wait for start signal (Port 4) Request the bus Wait for bus grant from arbiter Clear the BA counter Loop: write memory, wait for ACK, adjust counters, check for zero? Interrupt CPU and wait for INTA Lillevik 437s06-l11 University of Portland School of Engineering

FSM loop pseudo code execute Port1, Port2 for (wc = nn; wc != 0; wc--) { get the bus (Breq, Bgnt) drive the bus (Ben) wait for acknowledge (Ack) increment counters (BA, MA, WC) } Assert interrupt and wait for acknowledge Lillevik 437s06-l11 University of Portland School of Engineering

FSM input/outputs Clk, Reset Bgnt Breq FSM Port4 Ben Zero Count Ack Inta Int Port4 Clear Ack Lillevik 437s06-l11 University of Portland School of Engineering

FSM partial state diagram? Loop only Input Output Port4 Port4 a Reset Lillevik 437s06-l11 University of Portland School of Engineering

FSM state diagram? Input Output Port4 Port4 a Reset Lillevik 437s06-l11 University of Portland School of Engineering

Specific HD example Memory HD device buffer adr 27 adr 7 7+1 words System bus adr 0 adr 20 Lillevik 437s06-l11 University of Portland School of Engineering

HD buffer contents Sort of a marching one’s pattern Lillevik 437s06-l11 University of Portland School of Engineering

CPU program Initialize memory address counter to 0x20, word count to 0x07 Tell the DMA controller to start transferring data Do nothing Wait for interrupt Lillevik 437s06-l11 University of Portland School of Engineering

Find CPU program? Lillevik 437s06-l11 University of Portland School of Engineering

Find instructions across bus? Step Instruction (hex) Comment 1 a0120 Cpu writing 2 a0207 3 a0400 Cpu 4 62001 5 62102 6 62204 7 62308 8 62410 9 62520 10 62640 11 62780 12 Lillevik 437s06-l11 University of Portland School of Engineering

Lillevik 437s06-l11 University of Portland School of Engineering

FSM partial state diagram? Loop only Ack Breq Ben We will check for zero here Ack c d Bgnt Bgnt b e Port4 Count Breq Port4 a Reset Lillevik 437s06-l11 University of Portland School of Engineering

FSM State Diagram? b e c d f a Reset Port4 Bgnt Ack Zero Breq Ben Count Inta Int g Clear Input Output Lillevik 437s06-l11 University of Portland School of Engineering

Find CPU program? Lillevik 437s06-l11 University of Portland School of Engineering

Find instructions across bus? Step Instruction (hex) Comment 1 A0120 MA = 0x20 2 A0207 WC = 0x07 3 A0400 Start DMA transfers 4 62001 Mem[20] = 0x01 5 62102 Mem[21] = 0x02 6 62204 Mem[22] = 0x04 7 62308 Mem[23] = 0x08 8 62410 Mem[24] = 0x10 9 62520 Mem[25] = 0x20 10 62640 Mem[26] = 0x40 11 62780 Mem[27] = 0x80 12 Lillevik 437s06-l11 University of Portland School of Engineering