COMBINATIONAL LOGIC - 3

Dynamic Logic

Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors

Dynamic Gate Two phase operation Precharge (CLK = 0) Out Clk A B C Mp Me Clk Mp Out CL In1 In2 PDN In3 Clk Me For class handout Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

Dynamic Gate Two phase operation Precharge (Clk = 0) Out Clk A B C Mp Me off Clk Mp on 1 Out CL ((AB)+C) In1 In2 PDN In3 Clk Me off For lecture Evaluate transistor, Me, eliminates static power consumption on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

Dynamic CMOS Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.

Properties of Dynamic CMOS Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL CL being lower also contributes to power savings

Properties of Dynamic CMOS Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock

Dynamic 4 Input NAND Gate VDD Out In1 In2 In3 In4 f GND

Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL (1) A (2) Evaluate VOut Clk Me Precharge leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device. Charge stored on CL will leak away with time (input in low state during evaluation) Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks) PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths. Leakage sources Dominant component is subthreshold current

Solution to Charge Leakage Keeper Clk Mp Mkp CL A Out B Clk Me During precharge, Out is VDD and inverter out is GND, so keeper is on During evaluation if PDN is off, the keeper compensates for drained charge due to leakage. If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually Note Psc during switching period when PDN and keeper are both on simultaneously Same approach as level restorer for pass-transistor logic

Issues in Dynamic Design 2: Charge Sharing (redistribution) Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out CL A CA B=0 CB Clk CA initially discharged and CL fully charged. Me

Charge Sharing Example (redistribution) Clk Out = A xor B xor C Out CL=50fF A A Ca=15fF B Cb=15fF B B B Cc=15fF Cd=10fF C C Out = A xor B xor C What is the worst case change in voltage on node Out - assume all inputs are low during precharge and all internal capacitances are initially 0V Worst case is obtained by exposing the maximum amount of internal capacitance to the output node during evaluation. This happens when !A B C or A !B C 30/(30+50) * 2.5 V = 0.94 V so the output drops to 2.5 - 0.94 = 1.56 V Clk DV = 30/(30+50) * 2.5 V = 0.94 V Output drops to 2.5 - 0.94 = 1.56 V

Charge Sharing (redistribution) V DD Clk M p Out C L A M a X C a B = M b C b Clk M e C |V | Tp Must keep Vout < |VTp| a <  0.2 C DD V Tn – L

Solution to Charge Redistribution Clk Clk Mp Mkp Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

Issues in Dynamic Design 3: Backgate Coupling Clk Mp Out1 =1 Out2 =0 CL1 CL2 In A=0 B=0 Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces Clk Me Dynamic NAND Static NAND

Backgate Coupling Effect Due to clk feedthrough Out1 Due to backgate Voltage Clk Out2 Does not discharge to GND Out1 overshoots Vdd (2.5V) due to clock feedthrough And Out2 never quite makes it to GND In Time, ns

Issues in Dynamic Design 4: Clock Feedthrough p e V DD CLK Out A B C L a b X could potentially forward bias the diode 2.5V CLK overshoot out Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate.

Clock Feedthrough and Charge Sharing M p e V DD CLK Out A B C L a b X Clock feedthrough Clock feedthrough

Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)

Cascading Dynamic Gates V Clk Clk Clk Mp Mp Out2 Out1 In In Out1 VTn Clk Clk Me Me Out2 V Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. The second dynamic inverter turns off (PDN) when Out1 reaches VTn. Setting all inputs of the second gate to 0 during precharge will fix it. Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 -> 1 transition during the evaluation period t Only 0  1 transitions allowed at inputs!

Domino Logic Clk Clk Out1 Out2 In1 In4 PDN In2 PDN In5 In3 Clk Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1 Clk Me Clk Me

Why Domino? Like falling dominos! Ini PDN Inj Ini Inj PDN Ini PDN Inj Clk Clk Like falling dominos!

Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L H transition Input capacitance reduced – smaller logical effort Adding level restorer reduces leakage and Charge redistribution problem Optimise Inverter for fan-out First 32 bit micro (BellMAC 32) was designed in Domino logic Now a rather rare design style due to non-inverting logic only

Domino Manchester Carry Chain Adder P C i,0 1 G 2 3 4 f V DD M o,4 1.5 2.5 3.5 0.5

Designing with Domino Logic V V DD DD V DD Clk M Clk p M p M Out1 r Out2 In 1 In PDN In PDN 2 4 In 3 Can be eliminated! Clk M M e Clk e Inputs = 0 during precharge

Footless Domino The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage

Differential (Dual Rail) Domino off on Clk Clk Mp Mkp Mkp Mp Out = AB Out = AB 1 0 1 0 A !A !B B AND/NAND differential logic gate. The inputs and their complements come from other differential DR gates and thus all inputs are low during precharge and make a conditional transition from 0 to 1. Annotations show state during evaluate cycle (CLK = 1) Expensive - but can implement any arbitrary function. Use significant power since they have a guaranteed transition every single clock cycle (regardless of signal statistics, since either Out or !Out will transition from 0 to 1). Not ratioed (even though have a cross-coupled PMOS pair) Clk Me Solves the problem of non-inverting logic

np-CMOS Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me Also called zipper logic - In4 and In5 must be from PDN’s DEC alpha uses np-CMOS logic (Dobberpuhl) Have to size the PUN’s to equalize the delay to that of the PDN’s Really dense layouts and very high speed (20% faster than domino with the correct sizing) Reduced noise margin (as with any dynamic gate) Have two clock signals to generate and route - CLK and !CLK Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN

NORA Logic WARNING: Very sensitive to noise! Clk Clk Out1 In4 PUN In1 Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me NORA - no race CMOS to other PDN’s to other PUN’s WARNING: Very sensitive to noise!

np CMOS Adder V V V V CLK CLK S CLK CLK C A B B A A B C A B CLK CLK 1 C i 1 A B B 1 1 1 A 1 A B C 1 1 i 1 A 1 B CLK 1 CLK CLK C i 2 CLK V V DD DD V DD CLK CLK CLK B A C i 1 A B C i A A B B C i S CLK CLK CLK C i Carry Path

CMOS Circuit Styles - Summary Must consider area, performance, power, robustness (noise immunity), ease of design, system clocking requirements, fan-out, functionality, ease of testing

SEQUENTIAL LOGIC- I

Sequential Logic 2 storage mechanisms • positive feedback • charge-based

Naming Conventions In the text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edge-triggered elements flip-flops This leads to confusion however

Latch versus Register Latch Register stores data when clock is low stores data when clock rises D Q D Q Clk Clk Clk Clk D D Q Q

Latches

Latch-Based Design N latch is transparent when CLK = 0 P latch is transparent when CLK = 1 CLK N P Logic Latch Latch Logic

Timing Definitions CLK t Register t t D Q D DATA CLK STABLE t t Q DATA su hold D DATA CLK STABLE t t c  q Q DATA STABLE t

Characterizing Timing D  Q D Q D Q Clk Clk t t C  Q C  Q Register Latch

Maximum Clock Frequency CLk s ’ F F LOGIC Also: tcdreg + tcdlogic > thold tcd: contamination delay = minimum delay t p,comb T  tclk-Q + tp,comb + tsetup

Positive Feedback: Bi-Stability 1 V i 1 A C B o 2 = o1 Vi2 o 1 o V V 5 2 i V 1 o V 5 i 2 V

Meta-Stability Gain should be larger than 1 in the transition region