ALF Amdhal’s Law is Forever

Slides:



Advertisements
Similar presentations
Automatic Data Movement and Computation Mapping for Multi-level Parallel Architectures with Explicitly Managed Memories Muthu Baskaran 1 Uday Bondhugula.
Advertisements

Lecture 4 Introduction to Digital Signal Processors (DSPs) Dr. Konstantinos Tatas.
Multiprocessors— Large vs. Small Scale Multiprocessors— Large vs. Small Scale.
Challenges and Opportunities for System Software in the Multi-Core Era or The Sky is Falling, The Sky is Falling!
Chapter1 Fundamental of Computer Design Dr. Bernard Chen Ph.D. University of Central Arkansas.
Discussion. What is predictability? Is it another word for: “Degree of variance”, “Degree of analyzability”, “Repeatability”, “Determinism” What is the.
Instruction Level Parallelism (ILP) Colin Stevens.
Chapter Hardwired vs Microprogrammed Control Multithreading
 States that the number of transistors on a microprocessor will double every two years.  Current technology is approaching physical limitations. The.
Synergistic Processing In Cell’s Multicore Architecture Michael Gschwind, et al. Presented by: Jia Zou CS258 3/5/08.
Princess Sumaya Univ. Computer Engineering Dept. د. بســام كحـالــه Dr. Bassam Kahhaleh.
Chapter1 Fundamental of Computer Design Dr. Bernard Chen Ph.D. University of Central Arkansas Fall 2010.
1 Thread level parallelism: It’s time now ! André Seznec IRISA/INRIA CAPS team.
Multi-core architectures. Single-core computer Single-core CPU chip.
Compiler BE Panel IDC HPC User Forum April 2009 Don Kretsch Director, Sun Developer Tools Sun Microsystems.
Multi-Core Architectures
Lecture 1: Performance EEN 312: Processors: Hardware, Software, and Interfacing Department of Electrical and Computer Engineering Spring 2013, Dr. Rozier.
1 Thread level parallelism: It’s time now ! André Seznec IRISA/INRIA CAPS team.
Sogang University Advanced Computing System Chap 1. Computer Architecture Hyuk-Jun Lee, PhD Dept. of Computer Science and Engineering Sogang University.
CAPS project-team Compilation et Architectures pour Processeurs Superscalaires et Spécialisés.
Parallel Processing - introduction  Traditionally, the computer has been viewed as a sequential machine. This view of the computer has never been entirely.
Chapter 2 Parallel Architecture. Moore’s Law The number of transistors on a chip doubles every years. – Has been valid for over 40 years – Can’t.
Multi-core.  What is parallel programming ?  Classification of parallel architectures  Dimension of instruction  Dimension of data  Memory models.
CAPS project-team Compilation et Architectures pour Processeurs Superscalaires et Spécialisés.
VTU – IISc Workshop Compiler, Architecture and HPC Research in Heterogeneous Multi-Core Era R. Govindarajan CSA & SERC, IISc
Outline  Over view  Design  Performance  Advantages and disadvantages  Examples  Conclusion  Bibliography.
Chapter 1 — Computer Abstractions and Technology — 1 The Computer Revolution Progress in computer technology – Underpinned by Moore’s Law Makes novel applications.
Chapter 1 Performance & Technology Trends Read Sections 1.5, 1.6, and 1.8.
Multi-Core Development Kyle Anderson. Overview History Pollack’s Law Moore’s Law CPU GPU OpenCL CUDA Parallelism.
A few issues on the design of future multicores André Seznec IRISA/INRIA.
Morgan Kaufmann Publishers
Multi-core processors. 2 Processor development till 2004 Out-of-order Instruction scheduling Out-of-order Instruction scheduling.
Processor Level Parallelism. Improving the Pipeline Pipelined processor – Ideal speedup = num stages – Branches / conflicts mean limited returns after.
1 chapter 1 Computer Architecture and Design ECE4480/5480 Computer Architecture and Design Department of Electrical and Computer Engineering University.
CS6068 Week 2 Quiz. What are David Patterson’s Three Wall of Computer Architecture?
CAPS project-team Compilation et Architectures pour Processeurs Superscalaires et Spécialisés.
… begin …. Parallel Computing: What is it good for? William M. Jones, Ph.D. Assistant Professor Computer Science Department Coastal Carolina University.
DR. SIMING LIU SPRING 2016 COMPUTER SCIENCE AND ENGINEERING UNIVERSITY OF NEVADA, RENO Session 3 Computer Evolution.
Computer Science and Engineering Copyright by Hesham El-Rewini Advanced Computer Architecture CSE 8383 May 2, 2006 Session 29.
SSU 1 Dr.A.Srinivas PES Institute of Technology Bangalore, India 9 – 20 July 2012.
Processor Performance & Parallelism Yashwant Malaiya Colorado State University With some PH stuff.
“Processors” issues for LQCD January 2009 André Seznec IRISA/INRIA.
S. Pardi Frascati, 2012 March GPGPU Evaluation – First experiences in Napoli Silvio Pardi.
Computer Organization CS345 David Monismith Based upon notes by Dr. Bill Siever and from the Patterson and Hennessy Text.
Conclusions on CS3014 David Gregg Department of Computer Science
Lynn Choi School of Electrical Engineering
Software Coherence Management on Non-Coherent-Cache Multicores
Introduction Super-computing Tuesday
Welcome: Intel Multicore Research Conference
Chapter1 Fundamental of Computer Design
Parallel Processing - introduction
Multi-core processors
Morgan Kaufmann Publishers Large and Fast: Exploiting Memory Hierarchy
Chapter 4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures Topic 14 The Roofline Visual Performance Model Prof. Zhang Gang
COSC 3406: Computer Organization
Architecture & Organization 1
Morgan Kaufmann Publishers
The University of Texas at Austin
Introduction, Focus, Overview
Architecture & Organization 1
Parallel Processing Sharing the load.
Benjamin Goldberg Compiler Verification and Optimization
Embedded Computer Architecture 5SIA0 Overview
Chapter 1 Introduction.
Multi Core Processing What is term Multi Core?.
Introduction, Focus, Overview
Lecture 20 Parallel Programming CSE /27/2019.
CAPS project-team Compilation et Architectures pour Processeurs Superscalaires et Spécialisés.
If you build it, will they buy it?
Presentation transcript:

ALF Amdhal’s Law is Forever In PetaQCD

New technological context Where we come from ? CAPS (1994-2008) Architecture and compilation for high-end processors (GP and embedded/special purpose) Four successive positive evaluations Caps Entreprise start-up created in 2003 New technological context the multicore era

The ALF group A. Seznec, DR INRIA, microarchitecture P. Michaud, CR INRIA, microarchitecture I. Puaut, Pr Univ. Rennes I, worst case execution time F. Bodin, after sabbatical (exp. 2010), compilation E. Rohou, INRIA specialist engineer, compilation + 4 Ph.D students + 4 engineers

The advent of the multicore era Up to 2002, throwing transistors in uniprocessor was the most cost-effective path for « performance for the masses » Since 2002, progressively entering the multicore era is it « parallelism for the masses » ? Hardware: yes Applications: no

Context Hardware: 1000’s processors on a chip in 2015-2020 will be feasible. E.g. the 80-cores Intel Terascale prototype in 2006 Effective high performance on the chip is the issue Applications: every application will have to run on // hardware Architecture: defining the 2020’s manycore architecture Compilation: code generation/adaptation for manycores Performance predictability: predicting/guaranteeing performance on manycores A L F

Objectives within PetaQCD Understand issues on a Petaflops range applications Modelize future multi manycores particularly memory hierarchy to: explore dimensionning: Cores vs local memory/cache sizes Computing power vs bandwidth at all levels People: A. Seznec + PhD to be hired