EE 345S Real-Time Digital Signal Processing Lab Fall 2007 Lab #2 Generating a Sine Wave Using the Hardware & Software Tools for the TI TMS320C6713 DSP Wael Barakat

Outline Sine Wave Generation Outputting Methods Function Call Lookup Table Difference Equation Outputting Methods Polling Interrupts Direct Memory Access (DMA)

Sine Wave Generation One-sided discrete-time signal of frequency ω0 cos(ω0n)u[n] One-sided continuous-time signal of frequency ω0 cos(2πf0t)u(t) Using a sample frequency fs such that fs > 2.f0 Substitute t=nTs=n/fs cos(2π(f0/fs)n)u[n] ω0=2π(f0/fs) radians/sample

Sine Wave Generation Function Call: Use the C library function sin(x) whenever a sine value is needed, approximated as the ratio of 2 10th order polynomials in x Computation: 21 multiplications, 21 additions and 1 division Memory Usage: 22 coefficients and 1 intermediate variable (x) and one constant (2) Lookup Table: Pre-compute and store one period of samples, can even store one-half or one-quarter period and use symmetry. Frequency is ω0=2πN/L L is the period Interpolate stored values to get result at all frequencies No computation needed, just memory reads.

y[n] = (2 cos 0) y[n-1] - y[n-2] + x[n] - (cos 0) x[n-1] Sine Wave Generation Difference Equation: Input x[n] and output y[n] (zero IC’s) y[n] = (2 cos 0) y[n-1] - y[n-2] + x[n] - (cos 0) x[n-1] Results from z-transform of cos(ω0n)u[n] Computation: 2 multiplications and 3 additions Memory Usage: 2 coefficients, 2 previous values of y[n] and 1 previous value of x[n] Drawback is the build-up of error due to feedback

Outputting Methods Polling: means constantly monitoring a device, a flag or a register until its value changes. Poll XRDY (transmit ready) bit of the McBSP0 (Multi-Channel Buffered Serial Port) serial port until TRUE then write to DXR (data transmit register) of the McBSP1. If XRDY is TRUE, function returns the sample and the value 1, If XRDY is FALSE, function returns immediately without sending a sample and return the value 0.

Serial Port Transmitter CPU writes a 32-bit word to the DXR. XRDY flag is cleared whenever data is written to DXR. After a word is shifted out of XSR, a transfer of the DXR to the XSR is performed. XRDY flag is set. When XRDY is set, serial port transmitter sends an interrupt request (XINT) to CPU.

Serial Port Receiver Bits received serially into RSR. When word is complete it is transferred to RBR. RBR copied to DRR if it is empty. RRDY bit in SPCR is set when RSR is moved to DRR and is cleared when DRR is read. When RRDY is set, McBSP generates a CPU interrupt request (RINT).

Outputting Methods Polling: for ( ; ; ) // Infinite Loop { } x_left = scale*sin(angle_left); x_right = scale*sin(angle_right); // Increment phase angles of sine waves angle_left += delta_left; angle_right += delta_right; // Reduce angles modulo 2 pi so no overflow if (angle_left > 2.0*PI) angle_left -= 2.0*PI; if (angle_right > 2.0*PI) angle_right -= 2.0*PI; WriteSample( x_left, x_right ); } Multiply the sin() by a scale so that it doesn’t become 0 when it’s converted to integer since |sin()|<1 and floats less 1 are converted to 0

Outputting Methods Polling: void WriteSample( float left, float right) { Uint32 ileft  = (Uint32) left; Uint32 iright = (Uint32)right; Uint32 output; /* Combine ileft and iright into a 32-bit word */ output = (iright << 16) | (ileft & 0x0000ffff); /* DSK6713_AIC23_write polls the Ready flag of the serial port and returns true/false to indicate success. */ while(!DSK6713_AIC23_write(hCodec, output)); } Convert float to integer Combine both samples into a 32-bit word to transmit via McBSP1 Poll XRDY bit and write output to McBSP0 DXR

Outputting Methods Polling: Most of the time in the polling method is spent in the infinite loop waiting for the XRDY flag to get set, DSP is doing nothing, A more efficient approach is to let DSP run tasks in background (modulating/demodulating, coding/decoding…), So, serial port will interrupt background tasks when sample is received and needs to be transmitted.

Outputting Methods Interrupts: are signals from hardware/software indicating the need for attention or change of execution. C6713 DSP has a vectored priority interrupt controller that can handle 16 different interrupts: RESET interrupt has highest priority, cannot be masked, NMI (Non-Maskable Interrupt) has the second highest priority (used to notify DSP of serious hardware errors), 2 reserved maskable interrupts come next, 12 additional maskable interrupts (INT4-INT15) have the lowest priority.

Interrupts Interrupt Source Default Mappings Interrupt Control Registers

Outputting Methods Conditions for an interrupt to occur: Global Interrupt Enable bit (bit 0 of Control Status Register) must be set to 1. If GIE=0, no maskable interrupt can occur, Non-Maskable Interrupt Enable bit (in the Interrupt Enable Register) must be set to 1. If NMIE=0, no maskable interrupt can occur, Bit corresponding to desired interrupt must be set to 1 in Interrupt Enable Register. When interrupt occurs, corresponding bit in IFR (interrupt flag register) is set to 1. No higher priority interrupt flag should be set to 1 in IER.

Outputting Methods When CPU interrupt ‘n’ occurs, program execution jumps to byte offset 32×n in an Interrupt Service Table (IST) which contains 16 Interrupt Service Fetch Packets (ISFP) each containing 8 32-bit instructions. ISFP may contain an entire Interrupt Service Routine (ISR) or may branch to a larger one.

Outputting Methods When an interrupt occurs: DSP sets corresponding interrupt flag in IFR to 1, If GIE=NMIE=1 and no higher priority interrupts are pending, interrupt is serviced: GIE copied to PGIE and GIE is cleared, Flag bit in IFR is cleared indicating interrupt is serviced, Return address is put in the Interrupt Return Pointer (IRP), Execution jumps to corresponding ISFP entry, Service routine must save the CPU state and restore it on exit.

Outputting Methods /* Select McBSP1 transmit int for INT15 */ intr_map(CPU_INT15, ISN_XINT1); /* Hook our ISR to INT15 intr_hook(tx_isr, CPU_INT15); /* Clear old interrupts INTR_CLR_FLAG(CPU_INT15); /* Enable interrupts INTR_ENABLE(CPU_INT_NMI); /* Set INT15 bit in IER INTR_ENABLE(CPU_INT15); /* Turn on enabled ints INTR_GLOBAL_ENABLE();