A single-cycle MIPS processor As previously discussed, an instruction set architecture is an interface that defines the hardware operations which are available to software. Any instruction set can be implemented in many different ways. Over the next few weeks we’ll compare two important implementations. In a basic single-cycle implementation all operations take the same amount of time—a single cycle. In a pipelined implementation, a processor can overlap the execution of several instructions, potentially leading to big performance gains. May 28, 2019

Single-cycle implementation In lecture, we will describe the implementation a simple MIPS-based instruction set supporting just the following operations. We use MIPS because it is significantly easier to implement than x86. Today we’ll build a single-cycle implementation of this instruction set. All instructions will execute in the same amount of time; this will determine the clock cycle time for our performance equations. We’ll explain the datapath first, and then make the control unit. Arithmetic: add sub and or slt Data Transfer: lw sw Control: beq May 28, 2019 A single-cycle MIPS processor

Computers are state machines A computer is just a big fancy state machine. Registers, memory, hard disks and other storage form the state. The processor keeps reading and updating the state, according to the instructions in some program. Computers are state machines (or finite automata). State CPU May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor John von Neumann In the old days, “programming” involved actually changing a machine’s physical configuration by flipping switches or connecting wires. A computer could run just one program at a time. Memory only stored data that was being operated on. Then around 1944, John von Neumann and others got the idea to encode instructions in a format that could be stored in memory just like data. The processor interprets and executes instructions from memory. One machine could perform many different tasks, just by loading different programs into memory. The “stored program” design is often called a Von Neumann machine. May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Memories It’s easier to use a Harvard architecture at first, with programs and data stored in separate memories. To fetch instructions and read & write words, we need these memories to be 32-bits wide (buses are represented by dark lines here), so these are 230 x 32 memories. (We will ignore byte addressability for the moment.) Blue lines represent control signals. MemRead and MemWrite should be set to 1 if the data memory is to be read or written respectively, and 0 otherwise. When a control signal does something when it is set to 1, we call it active high (vs. active low) because 1 is usually a higher voltage than 0. For today, we will assume you cannot write to the instruction memory. Pretend it’s already loaded with a program, which doesn’t change while it’s running. Read address Instruction memory [31-0] Read address Write data Data memory MemWrite MemRead May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Instruction fetching The CPU is always in an infinite loop, fetching instructions from memory and executing them. The program counter or PC register holds the address of the current instruction. MIPS instructions are each four bytes long, so the PC should be incremented by four to read the next instruction in sequence. Read address Instruction memory [31-0] PC Add 4 2004 2004 2000 May 28, 2019 A single-cycle MIPS processor

Encoding R-type instructions A few weeks ago, we saw encodings of MIPS instructions as 32-bit values. Register-to-register arithmetic instructions use the R-type format. op is the instruction opcode, and func specifies a particular arithmetic operation (see the back of the textbook). rs, rt and rd are source and destination registers. An example instruction and its encoding: add $s4, $t1, $t2 op rs rt rd shamt func 6 bits 5 bits 000000 01001 01010 10100 00000 1000000 May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Registers and ALUs R-type instructions must access registers and an ALU. Our register file stores thirty-two 32-bit values. Each register specifier is 5 bits long. You can read from two registers at a time. RegWrite is 1 if a register should be written. Here’s a simple ALU with five operations, selected by a 3-bit control signal ALUOp. Read register 1 register 2 Write register data data 2 data 1 Registers RegWrite ALU ALUOp ALUOp Function 000 and 001 or 010 add 110 subtract 111 slt May 28, 2019 A single-cycle MIPS processor

Executing an R-type instruction 1. Read an instruction from the instruction memory. 2. The source registers, specified by instruction fields rs and rt, should be read from the register file. 3. The ALU performs the desired operation. 4. Its result is stored in the destination register, which is specified by field rd of the instruction word. Read register 1 register 2 Write register data data 2 data 1 Registers RegWrite Result Zero ALU ALUOp Read address Instruction [31-0] I [25 - 21] I [20 - 16] Instruction memory I [15 - 11] op rs rt rd shamt func 31 26 21 16 11 6 5 0 May 28, 2019 A single-cycle MIPS processor

Encoding I-type instructions The lw, sw and beq instructions all use the I-type encoding. rt is the destination for lw, but a source for beq and sw. address is a 16-bit signed constant. Two example instructions: lw $t0, –4($sp) sw $a0, 16($sp) op rs rt address 6 bits 5 bits 16 bits 100011 11101 01000 1111 1111 1111 1100 101011 11101 00100 0000 0000 0001 0000 May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Accessing data memory For an instruction like lw $t0, –4($sp), the base register $sp is added to the sign-extended constant to get a data memory address. This means the ALU must accept either a register operand for arithmetic instructions, or a sign-extended immediate operand for lw and sw. We’ll add a multiplexer, controlled by ALUSrc, to select either a register operand (0) or a constant operand (1). r1 M u x 1 r1 M u x 1 r1 r2 r2 r2 RegDst RegDst May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Accessing data memory For an instruction like lw $t0, –4($sp), the base register $sp is added to the sign-extended constant to get a data memory address. This means the ALU must accept either a register operand for arithmetic instructions, or a sign-extended immediate operand for lw and sw. We’ll add a multiplexer, controlled by ALUSrc, to select either a register operand (0) or a constant operand (1). Read address Write data Data memory MemWrite MemRead 1 M u x MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp (FFFC)hex (A37C)hex (FFFFFFFC)hex (0000A37C)hex May 28, 2019 12 A single-cycle MIPS processor

A single-cycle MIPS processor MemToReg The register file’s “Write data” input has a similar problem. It must be able to store either the ALU output of R-type instructions, or the data memory output for lw. We add a mux, controlled by MemToReg, to select between saving the ALU result (0) or the data memory output (1) to the registers. Read address Write data Data memory MemWrite MemRead 1 M u x MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor RegDst A final annoyance is the destination register of lw is in rt instead of rd. We’ll add one more mux, controlled by RegDst, to select the destination register from either instruction field rt (0) or field rd (1). op rs rt address lw $rt, address($rs) Read address Write data Data memory MemWrite MemRead 1 M u x MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Branches For branch instructions, the constant is not an address but an instruction offset from the current program counter to the desired address. beq $at, $0, L add $v1, $v0, $0 add $v1, $v1, $v1 j Somewhere L: add $v1, $v0, $v0 The target address L is three instructions past the beq, so the encoding of the branch instruction has 0000 0000 0000 0011 for the address field. Instructions are 4 bytes long, so the actual memory offset is 4*3=12 bytes. 000100 00001 00000 0000 0000 0000 0011 op rs rt address May 28, 2019 A single-cycle MIPS processor

The steps in executing a beq 1. Fetch the instruction, like beq $at, $0, offset, from memory. 2. Read the source registers, $at and $0, from the register file. 3. Compare the values by subtracting them in the ALU. 4. If the subtraction result is 0, the source operands were equal and the PC should be loaded with the target address, PC + 4 + (offset x 4). 5. Otherwise the branch should not be taken, and the PC should just be incremented to PC + 4 to fetch the next instruction sequentially. May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Branching hardware We need a second adder, since the ALU is already doing subtraction for the beq. 4 Shift left 2 PC Add M u x 1 PCSrc Read address Write data Data memory MemWrite MemRead MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp  PCSrc=1 branches to PC+4+(offset4).  PCSrc=0 continues to PC+4. Multiply constant by 4 to get offset. May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor The final datapath 4 Shift left 2 PC Add M u x 1 PCSrc Read address Write data Data memory MemWrite MemRead MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Control The control unit is responsible for setting all the control signals so that each instruction is executed properly. The control unit’s input is the 32-bit instruction word. The outputs are values for the blue control signals in the datapath. Most of the signals can be generated from the instruction opcode alone, and not the entire 32-bit word. To illustrate the relevant control signals, we will show the route that is taken through the datapath by R-type, lw, sw and beq instructions. May 28, 2019 A single-cycle MIPS processor

R-type instruction path The R-type instructions include add, sub, and, or, and slt. The ALUOp is determined by the instruction’s “func” field. 4 Shift left 2 PC Add M u x 1 PCSrc Read address Write data Data memory MemWrite MemRead MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor lw instruction path An example load instruction is lw $t0, –4($sp). The ALUOp must be 010 (add), to compute the effective address. 4 Shift left 2 PC Add M u x 1 PCSrc Read address Write data Data memory MemWrite MemRead MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor sw instruction path An example store instruction is sw $a0, 16($sp). The ALUOp must be 010 (add), again to compute the effective address. 4 Shift left 2 PC Add M u x 1 PCSrc Read address Write data Data memory MemWrite MemRead MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp May 28, 2019 A single-cycle MIPS processor

beq instruction path One sample branch instruction is beq $at, $0, offset. The ALUOp is 110 (subtract), to test for equality. The branch may or may not be taken, depending on the ALU’s Zero output 4 Shift left 2 PC Add M u x 1 PCSrc Read address Write data Data memory MemWrite MemRead MemToReg Instruction [31-0] I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite Sign extend ALUSrc Result Zero ALU ALUOp May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Control signal table sw and beq are the only instructions that do not write any registers. lw and sw are the only instructions that use the constant field. They also depend on the ALU to compute the effective memory address. ALUOp for R-type instructions depends on the instructions’ func field. The PCSrc control signal (not listed) should be set if the instruction is beq and the ALU’s Zero output is true. Operation RegDst RegWrite ALUSrc ALUOp MemWrite MemRead MemToReg add 1 010 sub 110 and 000 or 001 slt 111 lw sw X beq May 28, 2019 A single-cycle MIPS processor

Generating control signals The control unit needs 13 bits of inputs. Six bits make up the instruction’s opcode. Six bits come from the instruction’s func field. It also needs the Zero output of the ALU. The control unit generates 10 bits of output, corresponding to the signals mentioned on the previous page. You can build the actual circuit by using big K-maps, big Boolean algebra, or big circuit design programs. The textbook presents a slightly different control unit. Read address Instruction memory [31-0] Control I [31 - 26] I [5 - 0] RegWrite ALUSrc ALUOp MemWrite MemRead MemToReg RegDst PCSrc Zero May 28, 2019 A single-cycle MIPS processor

A single-cycle MIPS processor Summary A datapath contains all the functional units and connections necessary to implement an instruction set architecture. For our single-cycle implementation, we use two separate memories, an ALU, some extra adders, and lots of multiplexers. MIPS is a 32-bit machine, so most of the buses are 32-bits wide. The control unit tells the datapath what to do, based on the instruction that’s currently being executed. Our processor has ten control signals that regulate the datapath. The control signals can be generated by a combinational circuit with the instruction’s 32-bit binary encoding as input. On next slides, we’ll see the performance limitations of this single-cycle machine and discuss how to improve upon it. May 28, 2019 A single-cycle MIPS processor

The single-cycle design from last time Read address Instruction memory [31-0] Write data Data MemWrite MemRead 1 M u x MemToReg 4 Shift left 2 PC Add PCSrc Sign extend ALUSrc Result Zero ALU ALUOp I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] RegDst register 1 register 2 register data 2 data 1 Registers RegWrite A control unit (not shown) generates all the control signals from the instruction’s “op” and “func” fields. May 28, 2019 Multicycle datapath 27

The example add from last time Consider the instruction add $s4, $t1, $t2. Assume $t1 and $t2 initially contain 1 and 2 respectively. Executing this instruction involves several steps. The instruction word is read from the instruction memory, and the program counter is incremented by 4. The sources $t1 and $t2 are read from the register file. The values 1 and 2 are added by the ALU. The result (3) is stored back into $s4 in the register file. 000000 01001 01010 10100 00000 100000 op rs rt rd shamt func May 28, 2019 Multicycle datapath 28

How the add goes through the datapath PC+4 Add M u x 1 PCSrc Add PC 4 Shift left 2 RegWrite Read address Write data Data memory MemWrite MemRead 1 M u x MemToReg Read address Instruction memory [31-0] I [25 - 21] 01001 Read register 1 register 2 Write register data data 2 data 1 Registers 00...01 Result Zero ALU ALUOp I [20 - 16] 01010 00...10 M u x 1 ALUSrc M u x 1 RegDst I [15 - 11] 10100 Sign extend I [15 - 0] 00...11 May 28, 2019 Multicycle datapath 29

Performance of Single-cycle Design CPU timeX,P = Instructions executedP * CPIX,P * Clock cycle timeX = N * 1 * ??? May 28, 2019 Performance 30

Edge-triggered state elements In an instruction like add $t1, $t1, $t2, how do we know $t1 is not updated until after its original value is read? We’ll assume that our state elements are positive edge triggered, and are updated only on the positive edge of a clock signal. The register file and data memory have explicit write control signals, RegWrite and MemWrite. These units can be written to only if the control signal is asserted and there is a positive clock edge. In a single-cycle machine the PC is updated on each clock cycle, so we don’t bother to give it an explicit write control signal. Read register 1 register 2 Write register data data 2 data 1 Registers RegWrite Read address Write data Data memory MemWrite MemRead State CPU PC May 28, 2019 Multicycle datapath 31

The datapath and the clock On a positive clock edge, the PC is updated with a new address. A new instruction can then be loaded from memory. The control unit sets the datapath signals appropriately so that registers are read, ALU output is generated, data memory is read or written, and branch target addresses are computed. Several things happen on the next positive clock edge. The register file is updated for arithmetic or lw instructions. Data memory is written for a sw instruction. The PC is updated to point to the next instruction. In a single-cycle datapath everything in Step 2 must complete within one clock cycle, before the next positive clock edge. How long is that clock cycle? May 28, 2019 Multicycle datapath 32

Compute the longest path in the add instruction PC+4 Add M u x 1 PCSrc Add PC 4 Shift left 2 2 ns RegWrite 2 ns 0 ns Read address Write data Data memory MemWrite MemRead 1 M u x MemToReg Read address Instruction memory [31-0] I [25 - 21] Read register 1 register 2 Write register data data 2 data 1 Registers Result Zero ALU ALUOp I [20 - 16] M u x 1 ALUSrc M u x 1 RegDst 2 ns I [15 - 11] 0 ns 2 ns 1 ns Sign extend I [15 - 0] 0 ns 0 ns 2 ns May 28, 2019 Multicycle datapath 33

The slowest instruction... If all instructions must complete within one clock cycle, then the cycle time has to be large enough to accommodate the slowest instruction. For example, lw $t0, –4($sp) is the slowest instruction needing __ns. Assuming the circuit latencies below. M u x 1 Read address Instruction memory [31-0] Write data Data Sign extend Result Zero ALU I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] register 1 register 2 register data 2 data 1 Registers 2 ns 2 ns 0 ns 2 ns 0 ns 0 ns 1 ns 0 ns May 28, 2019 Multicycle datapath 34

The slowest instruction... If all instructions must complete within one clock cycle, then the cycle time has to be large enough to accommodate the slowest instruction. For example, lw $t0, –4($sp) needs 8ns, assuming the delays shown here. 8ns reading the instruction memory 2ns reading the base register $sp 1ns computing memory address $sp-4 2ns reading the data memory 2ns storing data back to $t0 1ns M u x 1 Read address Instruction memory [31-0] Write data Data Sign extend Result Zero ALU I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] register 1 register 2 register data 2 data 1 Registers 2 ns 2 ns 0 ns 2 ns 0 ns 0 ns 1 ns 0 ns May 28, 2019 Multicycle datapath 35

...determines the clock cycle time If we make the cycle time 8ns then every instruction will take 8ns, even if they don’t need that much time. For example, the instruction add $s4, $t1, $t2 really needs just 6ns. 6 ns reading the instruction memory 2 ns reading registers $t1 and $t2 1 ns computing $t1 + $t2 2 ns storing the result into $s0 1 ns M u x 1 Read address Instruction memory [31-0] Write data Data Sign extend Result Zero ALU I [15 - 0] I [25 - 21] I [20 - 16] I [15 - 11] register 1 register 2 register data 2 data 1 Registers 2 ns 1 ns 0 ns May 28, 2019 Multicycle datapath 36

(48% x 6ns) + (22% x 8ns) + (11% x 7ns) + (19% x 5ns) = 6.36ns How bad is this? With these same component delays, a sw instruction would need 7ns, and beq would need just 5ns. Let’s consider the gcc instruction mix from p. 189 of the textbook. With a single-cycle datapath, each instruction would require 8ns. But if we could execute instructions as fast as possible, the average time per instruction for gcc would be: (48% x 6ns) + (22% x 8ns) + (11% x 7ns) + (19% x 5ns) = 6.36ns The single-cycle datapath is about 1.26 times slower! Instruction Frequency Arithmetic 48% Loads 22% Stores 11% Branches 19% May 28, 2019 Multicycle datapath 37

It gets worse... We’ve made very optimistic assumptions about memory latency: Main memory accesses on modern machines is >50ns. For comparison, an ALU on an AMD Opteron takes ~0.3ns. Our worst case cycle (loads/stores) includes 2 memory accesses A modern single cycle implementation would be stuck at <10Mhz. Caches will improve common case access time, not worst case. Tying frequency to worst case path violates first law of performance!! “Make the common case fast” (we’ll revisit this often) May 28, 2019 Multicycle datapath 38

Summary Performance is one of the most important criteria in judging systems. Here we’ll focus on Execution time. Our main performance equation explains how performance depends on several factors related to both hardware and software. CPU timeX,P = Instructions executedP * CPIX,P * Clock cycle timeX It can be hard to measure these factors in real life, but this is a useful guide for comparing systems and designs. A single-cycle CPU has two main disadvantages. The cycle time is limited by the worst case latency. It isn’t efficiently using its hardware. Next time, we’ll see how this can be rectified with pipelining. May 28, 2019 Multicycle datapath 39