AGENDA Architecture Microprocessor Communication and Bus Timings Demultiplexing Address and Data Lines

Architecture of 8085 Reveals the internal logic of a Microprocessor 8085 Architecture consists of following blocks: ALU logic Register Logic Timing and Execution Logic Interrupt Logic Serial I/O Logic

Architecture of 8085

General Purpose Registers Register Section General Purpose Registers A, B, C, D, E, H, and L BC, DE, and HL Special Function Registers Program Counter Stack Pointer

Flag Register S Z P C X Sign Carry Zero Parity Auxiliary Carry AC P C Sign Carry Zero Parity Auxiliary Carry X - Unspecified

Timing and Control Unit Timing and Execution Logic Instruction Register Instruction Decoder Timing and Control Unit Control Signals

Timing and Execution Logic Control Signals READY, RD’,WR’,ALE Status Signals S0, S1, IO/M’ DMA Signals HOLD, HLDA RESET Signals RESET IN, RESET OUT

Consists of 5 interrupts with following properties: Interrupt Logic Consists of 5 interrupts with following properties: Priority Maskable and Non Maskable Vectored and Non – Vectored INTA is an output signal

Serial I/O Logic Supports serial I/O using 2 lines SID – Serial Input Data SOD – Serial Output Data

Mp communication and Bus Timings The instruction code 0100 1111 (4FH – MOV C, A) is stored in memory location 2005H. Illustrate the steps and the timing of data flow when it is being fetched

Mp Communication And Bus Timings Data Bus 4F Internal Data Bus Memory 2000 B C Instruction Decoder D E ALU H L 2005 4F 2005 SP PC Control Logic Address Bus 4F RD

Demultiplexing Address & Data Lines

What we studied in this session.. 8085 Architecture 8085 Communication and bus timings Demultiplexing Address & Data Lnes

Probable Questions.. Explain with a neat diagram, the architecture of 8085 microprocessor Explain the flag register of 8085. With a neat diagram, explain how to separate multiplexed address and data lines in 8085. What Signals are activated when I/O port at address ABCD H is read by 8085 ?

Thank You Q & A