COMPUTER ORGANIZATION AND ARCHITECTURE 15EM2001 COMPUTER ORGANIZATION AND ARCHITECTURE © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Introduction to computer System and its sub modules There are two basic types of electrical signals, namely, analog and digital. The analog signals are continuous in nature and digital signals are discrete in nature. The electronic device that works with continuous signals is known as analog device and the electronic device that works with discrete signals is known as digital device. We use ‘0’ to represent LOW and ‘1’ to represent HIGH. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Computer Architecture Computer architecture refers to those parameters of a computer system that are visible to a programmer or those parameters that have a direct impact on the logical execution of a program. Examples of architectural attributes include the instruction set, the number of bits used to represent different data types, I/O mechanisms, and techniques for addressing memory. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Computer Organization Computer organization refers to the operational units and their interconnections that realize the architectural specifications. Examples of organizational attributes include those hardware details transparent to the programmer, such as control signals, interfaces between the computer and peripherals, and the memory technology used. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Basic Computer Model and different units of Computer Central Processor Unit, Input Unit, Output Unit, Memory Unit © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Number System & Representation Decimal Number System (0-9) Octal Number System (0-7) Hexa-Decimal Number System (0-F) Binary Number System (0, 1) © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Representation of Real Number Binary representation of 41.6875 is 101001.1011 Therefore any real number can be converted to binary number system There are two schemes to represent real number : Fixed-point representation 2) Floating-point representation © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Fixed-point representation Binary representation of 41.6875 is 101001.1011 To store this number, we have to store two information, -- the part before decimal point and -- the part after decimal point. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Floating-point representation In this representation, numbers are represented by a mantissa comprising the significant digits and an exponent part of Radix R. The format is: Numbers are often normalized, such that the decimal point is placed to the right of the first non zero digit. For example, the decimal number, To store this number in floating point representation, we store 5236 in mantissa part and 3 in exponent part. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Signed Integer Range of natural numbers is 0 to 2n-1 By including negative numbers -2n-1-1 to 2n-1-1 If we consider 8-bit number, then range of natural number is from 0- 255 For signed integer range is from -127 to 127 Signed Magnitude Form If MSB = 0 then it is +ve and if MSB = 1 then it is –ve © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Representation of Signed Integer in 1’s complement form 01011100 10100011 11111111 By adding ‘1’ to the result, it is ‘0’ Representation of Signed Integer in 2’s complement form 10100100 100000000 © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Arithmetic & Logical Unit Consider an ALU which can perform four arithmetic operations and four logical operations To distinguish between arithmetic and logical operation, we may use a signal line, 0 - in that signal, represents an arithmetic operation and 1 - in that signal, represents a logical operation. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

4- bit Full Adder © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Binary Subtractor: © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Design of ALU © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Memory Unit RAM ROM Block Diagram of ROM Block Diagram of RAM © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Control Unit To execute an instruction, the control unit of the CPU must generate the required control signal in the proper sequence. To generate the control signal in proper sequence, a wide variety of techniques exist. Most of these techniques, however, fall into one of the two categories, Hardwired Control Microprogrammed Control © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Hardwired Control : In this hardwired control techniques, the control signals are generated by means of hardwired circuit. The main objective of control unit is to generate the control signal in proper sequence. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Eg: Programmable Logic Array © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Microprogrammed Control In microprogrammed control unit, the logic of the control unit is specified by a microprogram. sequencing through microinstructions generating control signals to execute each microinstruction. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Control Word (CW) : Control word is defined as a word whose individual bits represent the various control signal. The individual control words in this microprogram are referred to as microinstructions. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Machine Language A processor can understand and execute machine instructions. Such instructions are simply binary numbers stored in the computer. If a programmer wished to program directly in machine language, then it would be necessary to enter the program as binary data. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Assembly Language Assembly language is a programming language that is one step away from machine language. Typically, each assembly language instruction is translated into one machine instruction by the assembler. Assembly language is hardware dependent, with a different assembly language for each type of processor I1: Move R3, R7 /R3 ← (R7) I2: Load R8, (R3) /R8 ← Memory (R3) I3: Add R3, R3, 4 /R3 ← (R3) + 4 I4: Load R9, (R3) /R9 ← Memory (R3) I5: BLE R8, R9, L3 /Branch if (R9) > (R8) © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Load the contents of location 201 into the AC. N = I + J + K Load the contents of location 201 into the AC. 2. Add the contents of location 202 to the AC. 3. Add the contents of location 203 to the AC. 4. Store the contents of the AC in location 204. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Assembly Language Compiler Interpreter Linker Loader © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Addressing Modes The most common addressing techniques are: Immediate Direct Indirect Register Register Indirect Displacement Stack © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

To explain the addressing modes, the following notationis used: A = contents of an address field in the instruction that refers to a memory R = contents of an address field in the instruction that refers to a register EA = actual (effective) address of the location containing the referenced operand (X) = contents of location X © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Immediate Addressing Instruction Operand The simplest form of addressing is immediate addressing OPERAND = A Immediate Addressing Instruction Opcode Operand © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Direct Addressing Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Limited address space © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 5

Direct Addressing Diagram Instruction Address A Memory Operand © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 6

Indirect Addressing Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 7

Indirect Addressing Diagram Instruction Address A Memory Pointer to operand Operand © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 9

Register Addressing Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed Shorter instructions Faster instruction fetch © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 10

Register Addressing No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing Direct addressing © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 11

Register Addressing Diagram Instruction Register Address R Registers Operand © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 12

Register Indirect Addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2n) One fewer memory access than indirect addressing © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 13

Register Indirect Addressing Instruction Opcode Register Address R Memory Registers Pointer to Operand Operand © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 14

Displacement Addressing EA = A + (R) Address field hold two values A = base value R = register that holds displacement or vice versa © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 15

Displacement Addressing Diagram © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 16

Displacement Addressing Relative Addressing Base-Register Addressing Indexing auto-indexing auto-incrementing EA = A + (R) R = (R) + 1 © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Displacement Addressing auto-decrementing EA = A + (R) R = (R) – 1 If indexing is performed after the indirection, it is termed postindexing EA = (A) + (R) With preindexing, the indexing is performed before the indirection: EA = ( A + (R) ) © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Stack Addressing Operand is (implicitly) on top of stack e.g. ADD Pop top two items from stack and add © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 21

Instruction Set The operation of a CPU is determine by the instruction it executes, referred to as machine instructions or computer instructions. The collection of different instructions is referred as the instruction set of the CPU. Each instruction must contain the information required by the CPU for execution. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Opcodes are represented by abbreviations, called mnemonics, that indicate the operations 4-bits 6-bits 6-bits Opcode Operand1 Operand2 A simple instruction format © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

The instruction set of a CPU can be categorized as follows: 1. Data Processing 2. Data Storage 3. Data Movement 4. Control Types of Operands Addresses Numbers Characters Logical Data © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Types of Operations Data Transfer Arithmetic Logical Conversion Input Output [ I/O ] System Control Transfer Control © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Data Transfer Move (Transfer) --------Transfer word or block from source to destination Store ----------------------Transfer word from processor to memory Load (fetch) -------------Transfer word from memory to processor Exchange ----------------Swap contents of source and destination Clear (reset)------------- Transfer word of 0s to destination Set -------------------------Transfer word of 1s to destination Push -----------------------Transfer word from source to top of stack Pop -------------------------Transfer word from top of stack to destination © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

B. Arithmetic Add --------------Compute sum of two operands Subtract --------Compute difference of two operands Multiply ---------Compute product of two operands Divide -----------Compute quotient of two operands Absolute --------Replace operand by its absolute value Negate ----------Change sign of operand Increment ------Add 1 to operand Decrement -----Subtract 1 from operand © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

C. Logical AND -----------------------Performs the logical operation AND bitwise OR--------------------------Performs the logical operation OR bitwise NOT -----------------------Performs the logical operation NOT bitwise Exclusive OR -------------Performs the specified logical operation Exclusive-OR bitwise Test --------------------------Test specified condition; set flag(s) based on outcome Compare -------------------Make logical or arithmetic comparison Set flag(s) based on outcome Set Control Variables------Class of instructions to set controls for protection purposes, interrupt handling, timer control etc. Shift -----------------------Left (right) shift operand, introducing constant at end Rotate --------------------Left (right) shift operation, with wraparound end © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

D. Input/output Input (Read)----- Transfer data from specified I/O port or device to destination (e.g., main memory or processor register) Output (Write)----Transfer data from specified source to I/O port or device. Start I/O------------ Transfer instructions to I/O processor to initiate I/O operation. Test I/O --------------Transfer status information from I/O system to specified destination © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

E. System Control System control instructions are those which are used for system setting and it can be used only in privileged state. Typically, these instructions are reserved for the use of operating systems. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

F. Transfer of Control The most common transfer-of-control operations found in instruction set are: Branch Skip Procedure call. © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

BRP X ----Branch to location X if result is positive BRN X ---- Branch to location X if result is negative BRZ X----- Branch to location X is result is zero BRO X----- Branch to location X if overflow occurs © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Instruction Format Opcode Opcode Address Opcode Address1 Address2 Zero Address Instruction Opcode Address One Address Instruction Opcode Address1 Address2 Two Address Instruction Opcode Address1 Address2 Address3 Three Address Instruction Example: X = (A + B) * (C + D) © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Three address instructions ADD R1 , A , B R 1 <--M [ A ] + M [ B ] ADD R2 , C , D R 2 <--M [ C ] + M [ D ] MUL X , R1 , R2 M [ X ] <--R 1 * R 2 MOV R1 , A R 1 <--M [ A ] ADD R1 , B R 1 <--R 1 + M [ B ] MOV R2 , C R 2 <--M [ C ] ADD R2 , D R 2 <--R 2 + M [ D ] MUL R1 , R2 R 1 <--R 1 * R 2 MOV X , R1 M [ X ] <--R 1 Two address instructions © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

One address instructions LOAD A A C <- M [ A J ADD B A C <- A C + M [ B ] STORE T M [ T ] <- A C LOAD C A C <- M [ C ] ADD D A C <- A C + M [ D ] MUL T A C <- A C • M [ T ] STORE X M [ X ] <- A C © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Zero address instructions © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Stack Organization Block diagram of 64- word stack © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

Subroutine Calls Requirements Set PC to arbitrary address Return PC to instruction after call sequence Handle nested subroutine calls Save and restore caller’s registers Pass an arbitrary number of arguments Pass and return structures Allocate and de-allocate space for local variables © 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED

© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED