DeMorgan’s Law and Gates CMPE212 Discussion 9/19/2014 Patrick Sykes

In Lab Today Learn how to use the function generator and oscilloscope. We’ll connect the function generator and oscilloscope to check gate time delays. We’ll verify DeMorgan’s laws.

Digital Design Remember the mystery circuit from last discussion? This is known as a half-adder and used to add two single bits together. The design is not scaleable. For example, combining N half-adders to perform N bit addition.

Let’s Design

Verilog Practice We will be revisiting this circuit several times throughout the semester. Try to implement the Full Adder circuit in Verilog.

Full Adder continued Notice that our implementation now takes a third input, a carry-in Connecting multiple Full Adders can be used to do N bit addition. However, this creates an issue.

Time Delay There is currently a speed limit to our signals This causes a delay from the input of a circuit to the output For our purposes so far, the time delay is so short we don’t notice it.

Time Delay Critical path: The longest necessary path through a circuit In lab, we want to exaggerate the critical path There is a large critical path in our adder, all of the carrys There are ways to deal with this, which you will learn in class

DeMorgan’s Laws Get used to them because they’ll be very useful

Questions?