Day 26: November 10, 2010 Memory Periphery ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 26: November 10, 2010 Memory Periphery Penn ESE370 Fall2010 -- DeHon

Today Decode Sensing Penn ESE370 Fall2010 -- DeHon

Memory Bank Penn ESE370 Fall2010 -- DeHon

Row Select Logically a big AND May include an enable for timing in synchronous Penn ESE370 Fall2010 -- DeHon

Row Select How can we do better? Area Delay Match to pitch of memory row Penn ESE370 Fall2010 -- DeHon

Row Select Compute inversions outside array Just AND appropriate line (bit or /bit) Penn ESE370 Fall2010 -- DeHon

Row Select Share common terms Multi-level decode Penn ESE370 Fall2010 -- DeHon

Row Select Same number of lines Half as many AND inputs Penn ESE370 Fall2010 -- DeHon

Row Select: Precharge NAND Penn ESE370 Fall2010 -- DeHon

Sensing Penn ESE370 Fall2010 -- DeHon

Differential Sense Amp Penn ESE370 Fall2010 -- DeHon

Differential Sense Amp Penn ESE370 Fall2010 -- DeHon

“Inverter” Penn ESE370 Fall2010 -- DeHon

“Inverter” Input high Input low Ratioed like grounded P Pulls itself up Until Vdd-VTP Penn ESE370 Fall2010 -- DeHon

DC Transfer Function Penn ESE370 Fall2010 -- DeHon

Differential Sense Amp Penn ESE370 Fall2010 -- DeHon

Differential Sense Amp “Inverter” output controls PMOS for second inverter Sets PMOS operating point current Penn ESE370 Fall2010 -- DeHon

Differential Sense Amp View: Current mirror Biases where inverter operating Penn ESE370 Fall2010 -- DeHon

Differential Sense Amp View: adjusting the pullup load resistance Changing the trip point for “inverter” Penn ESE370 Fall2010 -- DeHon

DC Transfer /in with in=0.5V Penn ESE370 Fall2010 -- DeHon

DC Transfer Various in Penn ESE370 Fall2010 -- DeHon

After Inverter Penn ESE370 Fall2010 -- DeHon

Connect to Column Equalize lines during precharge Penn ESE370 Fall2010 -- DeHon

Singled-Ended Read Penn ESE370 Fall2010 -- DeHon

5T SRAM Penn ESE370 Fall2010 -- DeHon

Single Ended Need reference to compare against Want to look just like bit line Equalize with bit line Penn ESE370 Fall2010 -- DeHon

Split Bit Line Split bit-line in half Precharge/equalize both Word in only one half Only it switches Amplify difference Penn ESE370 Fall2010 -- DeHon

Open Bit Line Architecture For 1T DRAM Add dummy cells Charge dummy cells to Vdd/2 “read” dummy in reference half Penn ESE370 Fall2010 -- DeHon

Memory Bank Penn ESE370 Fall2010 -- DeHon

Admin Have memory cell Andrew office hours Wednesday and Thursday Add drivers and amps Andrew office hours Wednesday and Thursday Penn ESE370 Fall2010 -- DeHon

Idea Minimize area of repeated cell Compensate with periphery Amplification (restoration) Match periphery pitch to cell row/column Decode Sensing Writer Drivers Penn ESE370 Fall2010 -- DeHon