Stefano Zucca, Lodovico Ratti

Slides:

Advertisements

Similar presentations

1 1 Università degli Studi di Pisa, 2 INFN Pisa, 3 Scuola Normale Superiore di Pisa, 4 Università degli Studi di Pavia, 5 INFN Pavia, 6 Università degli.

Advertisements

G. RizzoSuperB WorkShop – 17 November R&D on silicon pixels and strips Giuliana Rizzo for the Pisa BaBar Group SuperB WorkShop Frascati-17 November.

G.Villani jan. 071 CALICE pixel Deep P-Well results Nwell 16 μm x 16 μm P-well 17 μm x 17 μm Collecting diodes 3.6 μm x 3.6 μm Bias: NWell 3.5V Diodes:

Thursday, May 10th, 2007 Calice Collaboration meeting --- A.-M. Magnan --- IC London 1 Progress Report on the MAPS ECAL R&D on behalf of the MAPS group:

Tera-Pixel APS for CALICE Progress meeting, 12 th July 2006 Jamie Crooks, Microelectronics/RAL.

August SGSS front end, Summary August 2008 Edwin Spencer, SCIPP1 SGST Preview SCIPP, UC Santa Cruz Andrey Martchovsky Gregory Horn Edwin Spencer.

5ns Peaking Time Transimpedance Front End Amplifier for the Silicon Pixel Detector in the NA62 Gigatracker E. Martin a,b J. Kaplon b, A. Ceccucci b, P.

NA62 front end Layout in DM option Jan Kaplon/Pierre Jarron.

NA62 front end architecture and performance Jan Kaplon/Pierre Jarron.

Rutherford Appleton Laboratory Particle Physics Department A Novel CMOS Monolithic Active Pixel Sensor with Analog Signal Processing and 100% Fill factor.

L.Royer– Calice DESY – July 2010 Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand R&D LPC Clermont-Fd dedicated to the.

CMOS technologies in the 100 nm range for rad-hard front-end electronics in future collider experiments V. Re a,c, L. Gaioni b,c, M. Manghisoni a,c, L.

Università degli Studi di Pavia and INFN Pavia

Preliminary measurements for the 8 channel prototype of SPD discriminator ASIC I.The 8 channel prototype. II.Status of the test. III.Noise. IV.Gain. V.Test.

Specifications & motivation 2  Lowering integration time would significantly reduce background  Lowering power would significantly reduce material budget.

1 Development of the input circuit for GOSSIP vertex detector in 0.13 μm CMOS technology. Vladimir Gromov, Ruud Kluit, Harry van der Graaf. NIKHEF, Amsterdam,

Analog Building Blocks for P326 Gigatracker Front-End Electronics

Valerio Re, Massimo Manghisoni Università di Bergamo and INFN, Pavia, Italy Jim Hoff, Abderrezak Mekkaoui, Raymond Yarema Fermi National Accelerator Laboratory.

General status and plan Carried out extensive testing, obtained working pixels and promising radiation tolerance, just submitted engineering run 2013.

65 nm CMOS analog front-end for pixel detectors at the HL-LHC

A. Rivetti Villa Olmo, 7/10/2009 Lepix: monolithic detectors for particle tracking in standard very deep submicron CMOS technologies. A. RIVETTI I.N.F.N.

CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC Gianluca Traversi 1,2

Fermilab Silicon Strip Readout Chip for BTEV

Eleuterio SpiritiILC Vertex Workshop, April On pixel sparsification architecture in 130nm STM technology ILC Vertex Workshop April 2008 Villa.

CERN PH MIC group P. Jarron 07 November 06 GIGATRACKER Meeting Gigatracker Front end based on ultra fast NINO circuit P. Jarron, G. Anelli, F. Anghinolfi,

TIMEPIX2 FE STUDIES X. Llopart. Summary of work done During summer I have been looking at a possible front end for Timepix2 The baseline schematic is.

L. Ratti a,b, M. Dellagiovanna a, L. Gaioni a,b, M. Manghisoni b,c, V. Re b,c, G. Traversi b,c, S. Bettarini d,e, F. Morsani e, G. Rizzo d,e a Università.

S.Zucca a,c, L. Gaioni b,c, A. Manazza a,c, M. Manghisoni b,c, L. Ratti a,c V. Re b,c, E. Quartieri a,c, G. Traversi b,c a Università degli Studi di Pavia.

Analog front-end for vertically integrated hybrid and monolithic pixels L. Ratti Università degli Studi di Pavia and INFN Pavia XV SuperB General Meeting.

Analog Front End For outer Layers of SVT (L.4 & L.5) Team:Luca BombelliPost Doc. Bayan NasriPh.D. Student Paolo TrigilioMaster student Carlo FioriniProfessor.

P. Name Nikhef Amsterdam Electronics- Technology Vladimir Gromov, NIKHEF, Amsterdam. GOSSIPO-3 Meeting March 31, More on the Preamplifier.

Analysis of 3D Stacked Fully Functional CMOS Active Pixel Sensor Detectors (1) Istituto Nazionale di Fisica Nucleare Sezione di Perugia – Italy Sezione.

Laboratorio di Strumentazione Elettronica Annual Report of Activities – a.a. 2009/2010 – October 15, 2010Phone Meeting – October 29, 2010 Characterization.

A Low-noise Front-end ASIC design based on TOT technique for Read-out of Micro-Pattern Gas Detectors Huaishen Li, Na Wang, Wei Lai, Xiaoshan Jiang 1 State.

The design of fast analog channels for the readout of strip detectors in the inner layers of the SuperB SVT 1 INFN Sezione di Pavia I Pavia, Italy.

M. Manghisoni, L. Ratti Università degli Studi di Pavia INFN Pavia

Valerio Re Università di Bergamo and INFN, Pavia, Italy

Ivan Peric, Christian Kreidl, Peter Fischer University of Heidelberg

10-12 April 2013, INFN-LNF, Frascati, Italy

KLOE II Inner Tracker FEE

Activities in Pavia/Bergamo on Layer0 pixels

L. Ratti Università degli Studi di Pavia INFN Pavia

Charge sensitive amplifier

Design and Characterization of a Novel, Radiation-Resistant Active Pixel Sensor in a Standard 0.25 m CMOS Technology P.P. Allport, G. Casse, A. Evans,

M. Manghisoni, L. Ratti, V. Re, V. Speziali, G. Traversi

INFN Pavia and University of Bergamo

V. Reb,c, C. Andreolia,c, M. Manghisonib,c, E. Pozzatia,c, L

Radiation Tolerance of a 0.18 mm CMOS Process

INFN Pavia / University of Bergamo

L. Ratti, M. Manghisoni Università degli Studi di Pavia INFN Pavia

HPD with external readout

A 3D deep n-well CMOS MAPS for the ILC vertex detector

L. Ratti V SuperB Collaboration Meeting

ALICE ITS Upgrade : Pixel chip design

Activities in Pavia/Bergamo on SVT strip readout and on Layer0 pixels

Mimoroma2 MAPS chip: all NMOS on pixel sparsification architecture

A Fast Binary Front - End using a Novel Current-Mode Technique

Lecture 16 ANNOUNCEMENTS OUTLINE MOS capacitor (cont’d)

Update on microstrip front-end and Layer0 pixel upgrade

MAPS with advanced on-pixel processing

Qualitative Discussion of MOS Transistors

Monolithic active pixel sensors in a 130 nm triple well CMOS process

Status of the CARIOCA project

Analog Front-end electronics for the outer layers of the SuperB SVT: design and expected performances Luca Bombelli1,2 on behalf of the SVT-SuperB Group.

EMT 182 Analog Electronics I

OmegaPix 3D IC prototype for the ATLAS upgrade SLHC pixel project 3D Meeting 19th March, 2010 A. Lounis, C. de La Taille, N. Seguin-Moreau, G.

Signal processing for High Granularity Calorimeter

Readout Electronics for Pixel Sensors

Readout Electronics for Pixel Sensors

Readout Electronics for Pixel Sensors

Presentation transcript:

Stefano Zucca, Lodovico Ratti INMAPS 0.18 um CMOS technology: front-end design status report Stefano Zucca, Lodovico Ratti Università di Pavia Dipartimento di Elettronica INFN Sezione di Pavia 11th March 2010 – Pavia

CHANNEL READOUT CHAIN Vbl=750 mV Imir=20 nA Cfb=5 fF C1=160 fF A preliminary design and layout of each block in the figure above has been carried out. All the simulations have been performed keeping CD=40 fF. Use of a mirror feedback configuration for C2 discharge instead of the transconductor in order to reduce the overall noise and threshold dispersion. 2

PERFORMANCE P=18 uW per pixel Tp=235 ns ENC=29 electrons (CD=40 fF) Threshold dispersion=13e (at the shaper output) Threshold dispersion=23e (including discriminator contribution) 15um NLI=1% Charge sensitivity = 900 mV/fC

TEMPERATURE VARIATION The channel readout has been simulated in the temperature range between 0°C and 80°C. Gain temperature coefficient = 70 uV/(°C fC)

DEPLETION REGION WIDTH (ISE) ISETCAD simulations have been performed in order to find out the depletion region width W as a function of the applied voltage.

DEPLETION REGION WIDTH (ISE) As expected, the depletion region width W is weakly dependent on the nwell diode voltage biasing (7 um @ Vnwell=0.5 V)

OPEN ISSUES AND FUTURE ACTIVITIES PSRR simulations. Pixel structure (shielding between analog and digital part?). Parallel run with standard resistivity epitaxial layer (strongly recommended by Renato Turchetta): useful to compare the two solutions. Almost ready for the analog channel layout (some preliminary block layout have been already performed). Further ISE TCAD simulations.

BACKUP SLIDES

35 Collecting electrodes 35 Analog 50 Digital 50

TEMPERATURE VARIATION This good result has been obtained by exploiting the change in the temperature coefficient in both p and nMOS Id-Vgs characteristics. MP1 operates in Vgs<0.65 V, while MN1 and MN2 in Vgs>0.65 V. The reduction of MP1 │Vth│ is compensated by Va increasing (in case of increasing temperature, and vice versa), keeping Imir almost constant.