CS-447– Computer Architecture M,W 10-11:20am Lecture 5 Instruction Set Architecture Sep 12th, 2007 Majd F. Sakr msakr@qatar.cmu.edu www.qatar.cmu.edu/~msakr/15447-f07/ Greet class

Hypothetical Machine Consider the following hypothetical machine: # registers = 16 {R0 to R15}  require 4-bits to address them (24 = 16) # memory locations = 256 {M0 to M255}  require 8-bits to address them (28 = 256)

Hypothetical Machine (cont’d) # instructions = 32 {Inst0 to Inst31}  require 5-bits to be controlled (25 = 32) where Inst15 = Add (instruction # 15) & Inst9 = Load (instruction # 9)

Example 1: Add R0, R4, R11 Add R0, R4, R11 ; R0 = R4 + R11 01111 0000 0100 1011 And to make it simpler to read and use we will use the Hex notation 0F 4 B And the output of the assembler would simply be the following machine code: 0F04B

The instruction 17-bit Instruction OpCode Destination Register 1 In fact, each piece of an instruction can be considered as an individual number, & placing these numbers side by side forms the instruction. OpCode Destination Register 1 Source Register 1 Source Register 2 5 bits 4 bits 17-bit Instruction

Example 2: Load R13, 127 Load R13, 127 ; R13 = (127) 01001 1101 0111 1111 And in the Hex notation 09 D 7 F And the output of the assembler would simply be the following machine code: 09D7F

The instruction 17-bit Instruction In fact, the instruction format Example: OpCode, Operand, Operand, Operand is fixed only for a specific operation OpCode Register Memory Address 5 bits 4 bits 8 bits 17-bit Instruction

Note When the OpCode consist of a memory R/W, the operand, Source Register 1 & 2 are combined to form the address field of the instruction. When the OpCode consist of an immediate instruction, the operand, Source Register 1 & 2 are combined to form the constant whenever that is required.

The Instruction OpCode: basic operation of the instruction Destination Register: register where the result of the operations will be loaded Source Register 1 & 2: registers where the data will be operated on

Instruction size = data word size As you can see from counting the number of bits, this hypothetical machine instruction takes exactly 17-bits which should be the same size as a data word.

Design by Starting with the Instruction Size We would like to design a machine with: Instruction size = 8 bits Instruction number = 8 No Operation Add Sub Branch Load Store Increment Decrement x 3-bits of the instruction word will be reserved to control the 8 desired instructions

Design by Starting with the Instruction Size So we are left with 5-bits for the operands, With which we can address at most: 32 (= 25) memory locations 32 (= 25) registers But if we chose to do so, we will be restricted in the number of operands in the instructions to one

Design by Starting with the Instruction Size On the other hand if we wish to have instructions with 2 explicit operands; that is still possible with the 5-bits left. x How ? ! ?

How ? ! ? x 3 4 5 6 7 Using bits 3 with 4 and bits 5 with 6 to address 4 registers. Bits Registers addressed # of Registers 3 with 4 R1, R2, R3, R4 4 5 with 6

2 operands addressing 4 registers with 2-bits each Results 8 Instructions 2 operands addressing 4 registers with 2-bits each 1 operand of 5-bits addressing 32 memory locations Note: # operands increases # registers decreases

Consider this Instruction Set Data processing Data storage Data movement Program flow control Sub 000 Load 010 Read 100 GoTo 110 Add 001 Store 011 Write 101 BranchIf 111

Execution of a simple program The following program was loaded in memory starting from memory location 0. 0000 Load R2, ML4 ; R2 = (ML4) = 5 = 1012 0001 Read R3, Input14 ; R3 = input device 14 = 7 0010 Sub R1, R3, R2 ; R1 = R3 – R2 = 7 – 5 = 2 0011 Store R1, ML5 ; store (R1) = 2 in ML5

The Program in Memory 0000 010100110 1 0001 100110100 2 0010 000011110 3 0011 011010111 4 0100 000000101 … Don’t care 14 1011 Input Port 15 1111 Output Port Address Content Load R2, ML4 010 10 0100 Read R3, Input14 100 11 Sub R1, R2 000 01 Store ML5 011 0101

... Load CPU 1 Load R2, ML4 ; 010100110 R1 R3 010100110 I.R. R2 P.C. 000000101 ... 1 P.C. Load CPU

... Read CPU 2 Read R3, Input14 ; 100110100 100110100 010100110 R1 R3 000000111 R2 000000101 ... 1 2 Read CPU

Sub R1, R3, R2 ; 000011110 100110101 000011110 R1 R3 000000010 000000111 R2 000000101 ... 2 3 000000101 000000111 Sub CPU

... Store CPU 4 Store R1, ML5 ; 011010111 Next Instruction 011010111 Don’t Care 000000010 000000111 R2 000000101 ... 3 4 Store CPU

In the Memory 5 0101 Don’t care 000000010 Before Program Execution 0000 010100110 1 0001 100110100 2 0010 000011110 3 0011 011010111 4 0100 000000101 5 0101 Don’t care … 14 1011 Input Port 15 1111 Output Port Address Content Before Program Execution After Program Execution 000000010

Instruction Formats Layout of bits in an instruction Includes OpCode Includes (implicit or explicit) operand(s) Usually more than one instruction format in an instruction set

Instruction Length Affected by and affects: Memory size Memory organization Bus structure CPU complexity CPU speed Trade off between powerful instruction types and saving space (bits).

Allocation of Bits Number of addressing modes Number of operands Register versus memory Number of registers Address range Address granularity

Displacement (Indexed) Stack Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack 2

Immediate Addressing Operand is part of instruction The address field points to the operand e.g. ADD 525 Add 525 to contents of accumulator 525 is the operand No memory reference to fetch data Fast Limited range 3

Immediate Addressing Diagram Instruction OpCode Operand Example: ADD 525 ; AC = AC + 525 In an Accumulator-Based machine, we would like to add 525 to the accumulator, the result will be stored in the accumulator itself. 4

Direct Addressing Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand 5

Direct Addressing (cont’d) Single memory reference to access data No additional calculations to work out effective address Limited address space 5

Direct Addressing Diagram Instruction Memory OpCode Operand Operand Example: ADD (Addr2) ; AC = AC + (2) ; (2) = 255 6

Indirect Addressing (1) Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator 7

Indirect Addressing (2) Large address space 2n where n = address word length May be nested, multilevel, cascaded e.g. EA = ((A)) Draw the diagram yourself Multiple memory accesses to find operand Hence slower 8

Indirect Addressing Diagram Instruction Memory OpCode Operand Pointer to Operand ADD ((1)) ; AC = AC + ((1)) ((1)) = (3) = 255 = operand Operand Memory 9

Register Addressing (1) Operand is held in register named in address field EA = R Limited number of registers Very small address field needed Shorter instructions Faster instruction fetch 10

Register Addressing (2) No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing C programming: register int a; 11

Register Addressing Diagram Registers Instruction OpCode Operand Operand ADD R3 ; AC = AC + R3 ; AC = AC + 255 12

Register Indirect Addressing Similar to indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2n) One fewer memory access than indirect addressing 13

Register Indirect Addressing Diagram Instruction Memory OpCode Operand Registers Operand Pointer to Operand Example: ADD (R3) ; AC = AC + (R3) = AC + (1) ; AC = AC + 255 14

Displacement Addressing EA = A + (R) Address field hold two values A = base value R = register that holds displacement or vice versa 15

Displacement Addressing Diagram Instruction Memory OpCode Register R Address A Operand Registers Pointer to Operand + ADD (R2, BaseAddress) ; AC = AC + ; (R2+BaseAddress) ; AC = AC + (1) = AC + 255

A version of displacement addressing R = Program counter, PC Relative Addressing A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC 17

Base-Register Addressing A holds displacement R holds pointer to base address R may be explicit or implicit 18

Good for accessing arrays Indexed Addressing A = base R = displacement EA = A + R Good for accessing arrays R++ 19

Combinations Postindex EA = (A) + (R) Preindex EA = (A+(R)) (Draw the diagrams) 20

Operand is (implicitly) on top of stack e.g. Stack Addressing Operand is (implicitly) on top of stack e.g. ADD Pop top two items from stack and add 21

Byte ordering – Big Endian Bytes are ordered left to right (starting at “big end”) Byte 0 at the leftmost (most significant) to byte 3 at the rightmost (least significant) 1 2 3 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Word 0 Word 1 Bit 31 Bit 0

Byte ordering – Little Endian Byte 3 at the leftmost (MSB) to byte 0 at the rightmost (LSB) Bytes are ordered right to left (starting at “little end”) 3 2 1 Byte 3 Byte 2 Byte 1 Byte 0 Byte 7 Byte 6 Byte 5 Byte 4 Word 0 Word 1 Bit 31 Bit 0

An Example ISA – IA32

Moving Data: IA32 Moving Data Operand Types movl Source,Dest: %eax %edx %ecx %ebx %esi %edi %esp %ebp Moving Data movl Source,Dest: Move 4-byte (“long”) word Lots of these in typical code Operand Types Immediate: Constant integer data Like C constant, but prefixed with ‘$’ E.g., $0x400, $-533 Encoded with 1, 2, or 4 bytes Register: One of 8 integer registers But %esp and %ebp reserved for special use Others have special uses for particular instructions Memory: 4 consecutive bytes of memory Various “address modes”

movl Operand Combinations Source Dest Src,Dest C Analog Reg movl $0x4,%eax temp = 0x4; Imm Mem movl $-147,(%eax) *p = -147; Reg movl %eax,%edx temp2 = temp1; movl Reg Mem movl %eax,(%edx) *p = temp; Mem Reg movl (%eax),%edx temp = *p; Cannot do memory-memory transfer with a single instruction

Simple Addressing Modes Normal (R) Mem[Reg[R]] Register R specifies memory address movl (%ecx),%eax Displacement D(R) Mem[Reg[R]+D] Register R specifies start of memory region Constant displacement D specifies offset movl 8(%ebp),%edx

Indexed Addressing Modes Most General Form D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Constant “displacement” 1, 2, or 4 bytes Rb: Base register: Any of 8 integer registers Ri: Index register: Any, except for %esp Unlikely you’d use %ebp, either S: Scale: 1, 2, 4, or 8 Special Cases (Rb,Ri) Mem[Reg[Rb]+Reg[Ri]] D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D] (Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]

Address Computation Examples %edx 0xf000 %ecx 0x100 Expression Computation Address 0x8(%edx) 0xf000 + 0x8 0xf008 (%edx,%ecx) 0xf000 + 0x100 0xf100 (%edx,%ecx,4) 0xf000 + 4*0x100 0xf400 0x80(,%edx,2) 2*0xf000 + 0x80 0x1e080

Some Arithmetic Operations Format Computation Two Operand Instructions addl Src,Dest Dest = Dest + Src subl Src,Dest Dest = Dest - Src imull Src,Dest Dest = Dest * Src sall Src,Dest Dest = Dest << Src Also called shll sarl Src,Dest Dest = Dest >> Src Arithmetic shrl Src,Dest Dest = Dest >> Src Logical xorl Src,Dest Dest = Dest ^ Src andl Src,Dest Dest = Dest & Src orl Src,Dest Dest = Dest | Src

Some Arithmetic Operations Format Computation One Operand Instructions incl Dest Dest = Dest + 1 decl Dest Dest = Dest - 1 negl Dest Dest = - Dest notl Dest Dest = ~ Dest

Another Example ISA, Y86 Program Registers Condition Codes Memory %eax %esi %ecx %edi OF ZF SF %edx %esp PC %ebx %ebp Program Registers Same 8 as with IA32. Each 32 bits Condition Codes Single-bit flags set by arithmetic or logical instructions OF: Overflow ZF: Zero SF:Negative Program Counter Indicates address of instruction Memory Byte-addressable storage array Words stored in little-endian byte order

Y86 Instructions Format 1--6 bytes of information read from memory Can determine instruction length from first byte Not as many instruction types, and simpler encoding than with IA32 Each accesses and modifies some part(s) of the program state

Encoding Registers Each register has 4-bit ID Same encoding as in IA32 Register ID 8 indicates “no register” Will use this in our hardware design in multiple places %eax %ecx %edx %ebx %esi %edi %esp %ebp 1 2 3 6 7 4 5

Instruction Example Addition Instruction Add value in register rA to that in register rB Store result in register rB Note that Y86 only allows addition to be applied to register data Set condition codes based on result e.g., addl %eax,%esi Encoding: 60 06 Two-byte encoding First indicates instruction type Second gives source and destination registers Generic Form Encoded Representation addl rA, rB 6 rA rB

Arithmetic and Logical Operations Instruction Code Function Code Refer to generically as “OPl” Encodings differ only by “function code” Low-order 4 bytes in first instruction word Set condition codes as side effect Add addl rA, rB 6 rA rB Subtract (rA from rB) subl rA, rB 6 1 rA rB And andl rA, rB 6 2 rA rB Exclusive-Or xorl rA, rB 6 3 rA rB

Move Operations Like the IA32 movl instruction Register --> Register rrmovl rA, rB 2 rA rB Immediate --> Register irmovl V, rB 3 8 rB V Register --> Memory rmmovl rA, D(rB) 4 rA rB D Memory --> Register mrmovl D(rB), rA 5 rA rB D Like the IA32 movl instruction Simpler format for memory addresses Give different names to keep them distinct

Jump Instructions Refer to generically as “jXX” jmp Dest 7 Jump Unconditionally Dest Refer to generically as “jXX” Encodings differ only by “function code” Based on values of condition codes Same as IA32 counterparts Encode full destination address Unlike PC-relative addressing seen in IA32 jle Dest 7 1 Jump When Less or Equal Dest jl Dest 7 2 Jump When Less Dest je Dest 7 3 Jump When Equal Dest jne Dest 7 4 Jump When Not Equal Dest jge Dest 7 5 Jump When Greater or Equal Dest jg Dest 7 6 Jump When Greater Dest

Stack Operations Decrement %esp by 4 pushl rA a rA 8 Decrement %esp by 4 Store word from rA to memory at %esp Like IA32 Read word from memory at %esp Save in rA Increment %esp by 4 popl rA b rA 8

Subroutine Call and Return call Dest 8 Dest Push address of next instruction onto stack Start executing instructions at Dest Like IA32 Pop value from stack Use as address for next instruction ret 9

Miscellaneous Instructions nop Don’t do anything Stop executing instructions IA32 has comparable instruction, but can’t execute it in user mode We will use it to stop the simulator halt 1