Consider the following code segment for a loop: int a = 3, b = 4;

Slides:

Advertisements

Similar presentations

Branch prediction Titov Alexander MDSP November, 2009.

Advertisements

Pipelining V Topics Branch prediction State machine design Systems I.

1 Pipelining(2) CDA 3101 Discussion Section Question 1 Identify all of the data dependencies and necessary forwarding in the following code. No.

Lecture 8 Dynamic Branch Prediction, Superscalar and VLIW Advanced Computer Architecture COE 501.

Pipelining and Control Hazards Oct

Computer Organization and Architecture (AT70.01) Comp. Sc. and Inf. Mgmt. Asian Institute of Technology Instructor: Dr. Sumanta Guha Slide Sources: Based.

Pipeline Hazards Pipeline hazards These are situations that inhibit that the next instruction can be processed in the next stage of the pipeline. This.

Chapter 12 CPU Structure and Function. CPU Sequence Fetch instructions Interpret instructions Fetch data Process data Write data.

Computer Organization and Architecture

CPE 731 Advanced Computer Architecture ILP: Part II – Branch Prediction Dr. Gheith Abandah Adapted from the slides of Prof. David Patterson, University.

EECS 470 Branch Prediction Lecture 6 Coverage: Chapter 3.

Review CPSC 321 Andreas Klappenecker Announcements Tuesday, November 30, midterm exam.

Computer Organization and Architecture The CPU Structure.

EECE476: Computer Architecture Lecture 20: Branch Prediction Chapter extra The University of British ColumbiaEECE 476© 2005 Guy Lemieux.

EECC551 - Shaaban #1 lec # 5 Fall Reduction of Control Hazards (Branch) Stalls with Dynamic Branch Prediction So far we have dealt with.

LRU Replacement Policy Counters Method Example

Pipelining Fetch instruction Decode instruction Calculate operands (i.e. EAs) Fetch operands Execute instructions Write result Overlap these operations.

EECC551 - Shaaban #1 lec # 7 Fall Hardware Dynamic Branch Prediction Simplest method: –A branch prediction buffer or Branch History Table.

Csci4203/ece43631 Review Quiz. 1)It is less expensive 2)It is usually faster 3)Its average CPI is smaller 4)It allows a faster clock rate 5)It has a simpler.

Chapter 12 CPU Structure and Function. Example Register Organizations.

Computer Architecture Instruction Level Parallelism Dr. Esam Al-Qaralleh.

Dynamic Branch Prediction

EENG449b/Savvides Lec /25/05 March 24, 2005 Prof. Andreas Savvides Spring g449b EENG 449bG/CPSC 439bG.

CIS 429/529 Winter 2007 Branch Prediction.1 Branch Prediction, Multiple Issue.

Pipelined Datapath and Control (Lecture #15) ECE 445 – Computer Organization The slides included herein were taken from the materials accompanying Computer.

Lecture 41: Review Session #3 Reminders –Office hours during final week TA as usual (Tuesday & Thursday 12:50pm-2:50pm) Hassan: Wednesday 1pm to 4pm or.

CH12 CPU Structure and Function

Computer Architecture Lecture 26 Fasih ur Rehman.

1 Dynamic Branch Prediction. 2 Why do we want to predict branches? MIPS based pipeline – 1 instruction issued per cycle, branch hazard of 1 cycle. –Delayed.

CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Pipelining Basics.

Lecture 17 Final Review Prof. Mike Schulte Computer Architecture ECE 201.

Final Review Prof. Mike Schulte Advanced Computer Architecture ECE 401.

Dynamic Branch Prediction

Data Prefetching Smruti R. Sarangi.

CS2100 Computer Organization

Computer Structure Advanced Branch Prediction

Dynamic Branch Prediction

Part IV Data Path and Control

CS 704 Advanced Computer Architecture

Test 2 review Lectures 5-10.

Samira Khan University of Virginia Nov 13, 2017

Test 2 review Lectures 5-10.

CMSC 611: Advanced Computer Architecture

Part IV Data Path and Control

CS 5513 Computer Architecture Pipelining Examples

The processor: Pipelining and Branching

TIME C1 C2 C3 C4 C5 C6 C7 C8 C9 I1 branch decode exec mem wb bubble

So far we have dealt with control hazards in instruction pipelines by:

Dynamic Hardware Branch Prediction

So far we have dealt with control hazards in instruction pipelines by:

Lecture 20: OOO, Memory Hierarchy

Data Prefetching Smruti R. Sarangi.

So far we have dealt with control hazards in instruction pipelines by:

So far we have dealt with control hazards in instruction pipelines by:

Pipelining: dynamic branch prediction Prof. Eric Rotenberg

Adapted from the slides of Prof

Dynamic Hardware Prediction

So far we have dealt with control hazards in instruction pipelines by:

So far we have dealt with control hazards in instruction pipelines by:

So far we have dealt with control hazards in instruction pipelines by:

So far we have dealt with control hazards in instruction pipelines by:

Chapter 11 Processor Structure and function

So far we have dealt with control hazards in instruction pipelines by:

CS 3853 Computer Architecture Pipelining Examples

Problem ??: (?? marks) Consider executing the following code on the MIPS pipelined datapath: add $t5, $t6, $t8 add $t9, $t5, $t4 lw $t3, 100($t9) sub $t2,

Computer Structure Advanced Branch Prediction

Presentation transcript:

Consider the following code segment for a loop: int a = 3, b = 4; int x; if (x is a multiplication of 3) <-- branch b1 increment a <-- b1 taken else <-- b1 not taken increment b Assume that the following list of 10 values of x is processed by 10 iterations of this code: 7, 6, 10, 11, 9, 5, 3, 13, 2, 17 Assume that a two-bit branch prediction scheme is used. For each iteration of the loop, show the prediction and state of the two-bit branch predictor (the predicted direction) and the actual branch direction of the b1 branch instructions. The first iteration has been filled in already. 1 = Taken, 0 = Not Taken. 00 = Strongly Not Taken (Initial state of 2-bit predictor), 01: weakly NT, 10: Strongly Taken, 11: weakly Taken. What is the misprediction rate for branch b1? Iteration 1 2 3 4 5 6 7 8 9 10 b1 (prediction /actual) 00 / /

Important topics Cache addressing; LRU replacement policy; AMAT Defining number of bits needed for PO, VPN, PFN in single/multi-level page tables. Pipeline design; Understanding data/control dependency; being able to draw the space-time diagram with and without forwarding… Single-bit/double-bit branch predictors