Lab 8 On-Chip Bus R91921012 林政廷 R91921061 林耿賢

Add verilog file to this project

CFGLNK Jumper

Download(execute procards.exe)

Logic Module0 Architecture 0xC200_0000~0xC20F_FFFF 0xC000_0000 0xC000_0004 LM_LOCK: 0x C000_0008 0xC300_0000 My IP 0xC000_0010 0xC000_0014 0xC000_000C LM0 0xC000_0000 LM1 0xD000_0000 LM2 0xE000_0000 LM3 0xF000_0000

Integrator Memory Map

Logic Module Registers

Clock Generator

Clock control signal assignment(1) Before writing to the oscillator registers, you must unlock them by writing the value 0x0000A05F to the LM_LOCK register. After writing the oscillator register, relock them by writing any value other than 0x0000A05F to the LM_LOCK register.

Clock control signal assignment(2)

LEDS There are eight general-purpose green LEDs. These are lit by driving the associated LED output pin LOW. A red LED is also provided to indicate a user-defined error condition. The Example 2 FPGA configuration supplied with the logic module provides the register LM_LEDS to control the LEDs

Reference Integrator/LM-XCV600E+ Integrator/LM-EP20K600E+ User Guide AMBA Specification(Rev 2.0)