Four Bit Adder Sum A Cin B Cout 10/9/2007 DSD,USIT,GGSIPU.

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Presentation transcript:

Four Bit Adder Sum A Cin B Cout 10/9/2007 DSD,USIT,GGSIPU

Half adder entity ha is Port ( x : in std_logic; y : in std_logic; s : out std_logic; c : out std_logic); end ha; architecture Behavioral of ha is begin s <= x xor y; c <= x and y; end Behavioral; 10/9/2007 DSD,USIT,GGSIPU

Full adder entity fa_comp is Port ( a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; carry : out std_logic); end fa_comp; 10/9/2007 DSD,USIT,GGSIPU

architecture Behavioral of fa_comp is component ha is Port ( x : in std_logic; y : in std_logic; s : out std_logic; c : out std_logic); end component; signal temp1,temp2,temp3 : std_logic; begin ha1 : ha port map (x => a, y =>b, s=>temp1, c=> temp2); ha2 : ha port map (x=>temp1, y =>cin, s=>sum, c =>temp3); carry <= temp2 or temp3; end Behavioral; 10/9/2007 DSD,USIT,GGSIPU

4-bit adder entity adder4bit is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); carryin : in std_logic; sum : out std_logic_vector(3 downto 0); carryout : out std_logic); end adder4bit; 10/9/2007 DSD,USIT,GGSIPU

architecture Behavioral of adder4bit is component fa_comp is Port ( a : in std_logic; b : in std_logic; cin : in std_logic; sum : out std_logic; carry : out std_logic); end component fa_comp; signal temp : std_logic_vector(2 downto 0); 10/9/2007 DSD,USIT,GGSIPU

begin u1 : fa_comp port map (a=>a(0),b=>b(0),cin =>carryin,sum=>sum(0),carry=>temp(0)); u2 : fa_comp port map (a=>a(1),b=>b(1),cin=>temp(0),sum=>sum(1),carry =>temp(1)); u3 : fa_comp port map (a=>a(2),b=>b(2),cin=>temp(1),sum=>sum(2),carry=>temp(2)); u4 : fa_comp port map (a=>a(3),b=>b(3),cin=>temp(2),sum=>sum(3),carry=>carryout); end Behavioral; 10/9/2007 DSD,USIT,GGSIPU