Lecture 12 Power Devices (2)

Slides:

Advertisements

Similar presentations

Lecture Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Introduction 1.

Advertisements

MICROWAVE FET Microwave FET : operates in the microwave frequencies

Field Effect Transistors

SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. Power MOSFET (3) SD Lab. SOGANG Univ. BYUNGSOO KIM.

FET ( Field Effect Transistor)

1 LINLITHGOW ACADEMY PHYSICS DEPARTMENT MOSFETs 2 MOSFETS: CONTENT STATEMENTS Describe the structure of an n-channel enhancement MOSFET using the terms:

Spring 2007EE130 Lecture 41, Slide 1 Lecture #41 QUIZ #6 (Friday, May 4) Material of HW#12 & HW#13 (Lectures 33 through 38) –MOS non-idealities, V T adjustment;

SOGANG UNIVERSITY SOGANG UNIVERSITY. SEMICONDUCTOR DEVICE LAB. Power MOSFETs SD Lab. SOGANG Univ. Doohyung Cho.

FET ( Field Effect Transistor)

Lecture 15 OUTLINE MOSFET structure & operation (qualitative)

EE415 VLSI Design The Devices: MOS Transistor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

LDMOS for RF Power Amplifiers

FET ( Field Effect Transistor)

Lecture 19 OUTLINE The MOSFET: Structure and operation

Chapter 28 Basic Transistor Theory. 2 Transistor Construction Bipolar Junction Transistor (BJT) –3 layers of doped semiconductor –2 p-n junctions –Layers.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Derivation of transistor characteristics.

MOS Capacitors MOS capacitors are the basic building blocks of CMOS transistors MOS capacitors distill the basic physics of MOS transistors MOS capacitors.

Field Effect Transistors By Er. S.GHOSH

Chapter 5: Field Effect Transistor

IC Process Integration

Field Effect Transistors

Lecture 23 OUTLINE The MOSFET (cont’d) Drain-induced effects Source/drain structure CMOS technology Reading: Pierret 19.1,19.2; Hu 6.10, 7.3 Optional Reading:

1 Chapter 5. Metal Oxide Silicon Field-Effect Transistors (MOSFETs)

Midterm 2 performance Full points is 48. Average is

Conductors – many electrons free to move

4H-SIC DMOSFET AND SILICON CARBIDE ACCUMULATION-MODE LATERALLY DIFFUSED MOSFET Archana N- 09MQ /10/2010 PSG COLLEGE OF TECHNOLOGY ME – Power Electronics.

Introduction to semiconductor technology. Outline –6 Junctions Metal-semiconductor junctions –6 Field effect transistors JFET and MOS transistors Ideal.

Field Effect Transistors

BJT transistors FET ( Field Effect Transistor) 1. Unipolar device i. e. operation depends on only one type of charge carriers (h or e) 2. Voltage controlled.

FET ( Field Effect Transistor) 1.Unipolar device i. e. operation depends on only one type of charge carriers (h or e) 2.Voltage controlled.

The Devices: MOS Transistor

UNIT II : BASIC ELECTRICAL PROPERTIES

MAHATMA PHULE A.S.C. COLLEGE, PANVEL Field Effect Transistor

Power MOSFET Pranjal Barman.

MOSFET The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a semiconductor device which is widely used for switching and amplifying.

Field Effect Transistors: Operation, Circuit Models, and Applications

Instrumentation & Power Electronic Systems

Recall Last Lecture Common collector Voltage gain and Current gain

DMT 241 – Introduction to IC Layout

Metal Semiconductor Field Effect Transistors

GOVERMENT ENGINEERING COLLEGE

Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET

Lecture 20 OUTLINE The MOSFET (cont’d) Qualitative theory

Lecture 12 Power Devices (2)

Intro to Semiconductors and p-n junction devices

Semiconductor Transistors

6.3.3 Short Channel Effects When the channel length is small (less than 1m), high field effect must be considered. For Si, a better approximation of field-dependent.

HW#10 will be posted tonight

Lecture 16 ANNOUNCEMENTS OUTLINE MOS capacitor (cont’d)

Lecture 19 OUTLINE The MOSFET: Structure and operation

Notes on Diodes 1. Diode saturation current:

Week 9a OUTLINE MOSFET ID vs. VGS characteristic

Optional Reading: Pierret 4; Hu 3

Sung June Kim Chapter 19. MODERN FET STRUCTURES Sung June Kim

Reading: Finish Chapter 19.2

MOSFET POWERPOINT PRESENTATION BY:- POONAM SHARMA LECTURER ELECTRICAL

MOSFETs - An Introduction

Lecture 19 OUTLINE The MOS Capacitor (cont’d) The MOSFET:

Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET

Week 9a OUTLINE MOSFET ID vs. VGS characteristic

LECTURE # 8 FIELD EFFECT TRANSISTOR (FET)

Lecture #17 (cont’d from #16)

Lecture 20 OUTLINE The MOSFET (cont’d) Qualitative theory

Lecture 19 OUTLINE The MOS Capacitor (cont’d) The MOSFET:

Lecture #15 OUTLINE Diode analysis and applications continued

Subject Name: Electronic Circuits Subject Code:10cs32

Microelectronics, BSc course

MOSCAP Non-idealities

Solid State Electronics ECE-1109

Presentation transcript:

Lecture 12 Power Devices (2) Si Power MOSFET VMOSFET UMOSFET DMOSFET LDMOSFET V=Vertical

DMOSFET D: Diffused

UMOSFET U=U-groove

Forward blocking capability - Gate is short to source; no surface channel p-base-n-drift-layer junction become revers-biased and supports the positive drain voltage The peak p-base doping controls VT. Typical 2-3 V. nAP=1E17/cm3

Threshold voltage (2-3V) Ideal Model: More realistic model:

Channel Resistance Pinch off at VD=VG-VT >>>>> Saturation

Specific on-resistance (DMOSFET) The ideal Ron,sp for 50 V could be 0.1 mΩ-cm2

Si LDMOSFET For wireless base-station RF power amplifier a few GHz 10-100 W power output Motorala is the primary supplier

Rscont Rp-ch-cont Rdcont RLDD Rch Rshunt Rp+-sub SiO2 n+ p-channel n p- epi p+ sub p-channel SiO2 n 1u

Equivalent Circuit of RF LDMOSFET Rd Cgd Rg GmVgs Cds Vout Cgs Vin Rs Feature Low Rg(thicker TiSi2), Rshunt(enhanced p-channel), Rs(heavier n+ source & thinner substrate) Low Cgs in ARF4 (0.6u); Low Cgd due to less gate/LDD area & shallow LDD junction; Low Cds due to buffered drain Reduced Hot-carrier effect due to lower E-field in channel, improved gate oxide, and buffered drain

Layout of Single Metal Approach (Approach1-2) 1,330um 5,400um

Approach 3-4: 2-layer metal with gate strapping L60u &L100u 1,330um 5,400um

Package of AGR19090 LDMOS Package Output Capacitor Integrated Standoff LDMOS Die Input Capacitor

Handle approach devices Si (200 m) Polyimid Si (7-50 m) Cu heat sink Solder Layouts: 50u gate finger structure 50u gate finger structure with V-groove outside the active area 3x100u gate finger with metal stack and rotated gate strips(Mot.) 5x100u with our approach

Simulation of Dummy Gated LDMOS Equal-potential line contours of conventional LDMOS (ARF3, ARF4, Motorola) Equal-potential line contours of dummy gated LDMOS

Simulation of Dummy Gated LDMOS Electric field contours of conventional LDMOS (ARF3, ARF4, Motorola) Electric field contours of dummy gated LDMOS

Electric field distribution along the surface of LDMOS, and DG-LDMOS Channel LDD LDMOS DG-LDMOS Electric field distribution along the surface of LDMOS, and DG-LDMOS

MRF284 DCIV pre/post HCI

Homework: Read and study Chapter 4 Power Device pp Homework: Read and study Chapter 4 Power Device pp.203-220 “Modern Semiconductor Device Physics”