Surrogate Modeling for Predicting FPGA Place and Route Paritosh Dande Faculty: Dr. Rhett Davis, Dr. Paul Franzon NC State University Department of Electrical and Computer Engineering Backend tools have input settings which the algorithms use to converge to an output. Mapping the relationship between the inputs and outputs speeds up the place and route by predicting the input knobs settings for the desired outputs. This reduces the time taken by tools to converge to an output. 1. Introduction 6. Root Relative Square Error (RRSE) Python is used to automate the environment. Place and Route is done using Altera Quartus 17.0. Design used is CORTEX-M0DS. Surrogate Modeling is used to create models using ANN Genetic model. 2. Method 7. Results Board- 5CGXFC9E6F35C7 Utilization - 1.7% - 1.8% Board - 5CEFA2F23C8 Utilization- 20.8% 21.74% 58ns 51ns 35ns 40ns These graphs show the relationship between clock period and utilization as inputs and ALM’s and Registers used as outputs. As the utilization increases, the design saturates at a lower Clock Period and expected relationship can be seen in the models generated. 3. CORTEX-M0DS Design Implements a primary memory system and system bus interface. 32 bit processor and implements the ARMv6-M architecture.[1] Total number of pins – 136 4. Cyclone V Family FPGA Architecture Basic building block of Cyclone V Device architecture. Each ALM has two 6 Input LUT, adders and registers to implement functions.[2] 3D Surrogate models using utilization rate and clock rate as inputs. Classification model using a set of designs. 8. Future Scope Date points for an FPGA Board – 300 Time taken to generate dataset – 30 hours Inputs - Clock Period, Utilization on FPGA Board Outputs - Number of ALM’s used, Number of Registers used, Setup Slack, Hold Slack Time required to train – 6 hours Process corner - Fast 1100mv 0C corner 5. Training Data Model 9. References ARM CORTEXM0 Design start Release Note (2010). Altera Cyclone V Documentation. Bowen Li, Dr. Paul Franzon, Machine Learning in Physical Design.