Chapter 14 Arithmetic Circuits (II): Multiplier Rev. 1.0 05/12/2003 EE141 Chapter 14 Arithmetic Circuits (II): Multiplier Rev. 1.0 05/12/2003 Rev. 2.0 06/05/2003 Rev. 2.1 06/12/2003

Binary Multiplication

Binary Multiplication

Array Multiplier

MxN Array Multiplier — Critical Path

Wallace-Tree Multiplier

Wallace-Tree Multiplier

Multipliers —Summary Identify Critical Paths Possible techniques for speed up: Multiplier Encoding (Booth encoding) Wallace Tree Multiplier Pipelining (multi-phase multiplication)

Shifters

The Binary Shifter

The Barrel Shifter Area Dominated by Wiring

4x4 barrel shifter Widthbarrel ~ 2 pm M

Logarithmic Shifter

0-7 bit Logarithmic Shifter 3 2 1 Out3 Out2 Out1 Out0

Summary Datapath designs are fundamentals for high-speed DSP, Multimedia, Communication digital VLSI designs. Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint. For details, check “Advanced VLSI” notes, or “Computer Arithmetic” textbooks