11.2.3 High-Low Guessing Game

Clock.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Clockdiv IS PORT ( Clk25Mhz: IN STD_LOGIC; Clk: OUT STD_LOGIC); END Clockdiv; ARCHITECTURE Behavior OF Clockdiv IS -- CONSTANT max: INTEGER := 1000; -- minimum to debounce switch CONSTANT max: INTEGER := 5000000; -- good to see FSM states -- CONSTANT max: INTEGER := 10000000; -- 10000000; = 1sec CONSTANT half: INTEGER := max/2; SIGNAL count: INTEGER RANGE 0 TO max; BEGIN PROCESS WAIT UNTIL Clk25Mhz'EVENT and Clk25Mhz = '1'; IF count < max THEN count <= count + 1; ELSE count <= 0; END IF; IF count < half THEN Clk <= '0'; Clk <= '1'; END PROCESS; END Behavior;

Bcd.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BCD IS PORT ( in_bcd: IN std_logic_vector(3 DOWNTO 0); segs: OUT std_logic_vector(1 TO 7)); END BCD; ARCHITECTURE Behavioral OF BCD IS BEGIN PROCESS(in_bcd) CASE in_bcd IS -- 0=on; 1=off WHEN "0000" => segs <= "0000001"; -- 0 WHEN "0001" => Segs <= "1001111"; -- 1 WHEN "0010" => Segs <= "0010010"; -- 2 WHEN "0011" => Segs <= "0000110"; -- 3 WHEN "0100" => Segs <= "1001100"; -- 4 WHEN "0101" => Segs <= "0100100"; -- 5 WHEN "0110" => Segs <= "0100000"; -- 6 WHEN "0111" => Segs <= "0001111"; -- 7 WHEN "1000" => Segs <= "0000000"; -- 8 WHEN "1001" => Segs <= "0001100"; -- 9 WHEN "1010" => Segs <= "0001000"; -- A WHEN "1011" => Segs <= "1100000"; -- b WHEN "1100" => Segs <= "0110001"; -- C WHEN "1101" => Segs <= "1000010"; -- d WHEN "1110" => Segs <= "0110000"; -- E WHEN "1111" => Segs <= "0111000"; -- F WHEN OTHERS => Segs <= "1111111"; -- all off END CASE; END PROCESS; END Behavioral;

Bin_to_bcd.vhd IF (n >= 90) THEN IF (n >= 100) THEN bcd_tenth <= "1001"; ten := 90; ELSIF (n >= 80) THEN bcd_tenth <= "1000"; ten := 80; ELSIF (n >= 70) THEN bcd_tenth <= "0111"; ten := 70; ELSIF (n >= 60) THEN bcd_tenth <= "0110"; ten := 60; ELSIF (n >= 50) THEN bcd_tenth <= "0101"; ten := 50; ELSIF (n >= 40) THEN bcd_tenth <= "0100"; ten := 40; ELSIF (n >= 30) THEN bcd_tenth <= "0011"; ten := 30; ELSIF (n >= 20) THEN bcd_tenth <= "0010"; ten := 20; ELSIF (n >= 10) THEN bcd_tenth <= "0001"; ten := 10; ELSE bcd_tenth <= "0000"; ten := 0; END IF; unit := n - ten; bcd_unit <= CONV_STD_LOGIC_VECTOR(unit,4); END Process; END Behavioral; -- this program converts an 8-bit unsigned value to two BCD values -- if number >= 200, the decimal point for the tenth digit is on -- if 200 > number >= 100, the decimal point for the unit digit is on -- if number < 99, the two decimal digits will be separated into two BCD values LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE ieee.std_logic_unsigned.all; -- for CONV_INTEGER() USE IEEE.std_logic_arith.all; -- for CONV_STD_LOGIC_VECTOR() ENTITY bin_to_bcd IS PORT ( binary: IN STD_LOGIC_VECTOR(7 DOWNTO 0); point200, point100: OUT STD_LOGIC; bcd_tenth, bcd_unit: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END bin_to_bcd; ARCHITECTURE Behavioral OF bin_to_bcd IS BEGIN PROCESS(binary) VARIABLE n: integer RANGE 0 TO 255; VARIABLE ten: integer RANGE 0 TO 99; VARIABLE unit: integer RANGE 0 TO 9; n := CONV_INTEGER(binary); IF (n >= 200) THEN point200 <= '1'; n := n - 100; ELSE point200 <= '0'; END IF; IF (n >= 100) THEN point100 <= '1'; point100 <= '0';

Bin2dec.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bin2dec IS PORT ( input: IN STD_LOGIC_VECTOR(7 DOWNTO 0); PointN200,PointN100: OUT STD_LOGIC; aN10,bN10,cN10,dN10,eN10,fN10,gN10,aN1,bN1,cN1,dN1,eN1,fN1,gN1: OUT STD_LOGIC); END bin2dec; ARCHITECTURE Structural OF bin2dec IS COMPONENT bin_to_bcd PORT ( binary: IN STD_LOGIC_VECTOR(7 DOWNTO 0); point200, point100: OUT STD_LOGIC; bcd_tenth, bcd_unit: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT BCD PORT ( in_bcd: IN std_logic_vector(3 DOWNTO 0); segs: OUT std_logic_vector(1 TO 7)); SIGNAL c_bcd1,c_bcd10: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c_point200,c_point100: STD_LOGIC; SIGNAL c_seg10,c_seg1: STD_LOGIC_VECTOR(1 TO 7); BEGIN U1: bin_to_bcd PORT MAP (input,c_point200,c_point100,c_bcd10,c_bcd1); U2: BCD PORT MAP (c_bcd10,c_seg10); U3: BCD PORT MAP (c_bcd1,c_seg1); PointN200 <= NOT c_point200; PointN100 <= NOT c_point100; aN10 <= c_seg10(1); bN10 <= c_seg10(2); cN10 <= c_seg10(3); dN10 <= c_seg10(4); eN10 <= c_seg10(5); fN10 <= c_seg10(6); gN10 <= c_seg10(7); aN1 <= c_seg1(1); bN1 <= c_seg1(2); cN1 <= c_seg1(3); dN1 <= c_seg1(4); eN1 <= c_seg1(5); fN1 <= c_seg1(6); gN1 <= c_seg1(7); END Structural;

Mp.vhd BEGIN next_state_logic: PROCESS(reset, clock) IF(reset = '1') THEN state <= s0; Largest <= (OTHERS => '0'); ELSIF(clock'EVENT AND clock = '1') THEN CASE state IS WHEN s0 => X <= input; IF (enter = '1') THEN state <= s1; ELSE state <= s0; END IF; WHEN s1 => IF (X = "00000000") THEN state <= s3; ELSIF (X > Largest) THEN state <= s2; ELSIF (enter = '0') THEN state <= s0; ELSE state <= s1; END IF; WHEN s2 => Largest <= X; IF (enter = '0') THEN state <= s0; ELSE state <= s2; END IF; WHEN s3 => state <= s3; WHEN OTHERS => END CASE; END PROCESS; -- all the output signals must be assigned in a process without -- the IF Clock'EVENT condition, otherwise they will be treated -- as storage elements and therefore cannot be tri-stated output_logic: PROCESS(state) output <= Largest; done <= '1'; done <= '0'; END FSMD; Mp.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY mp IS PORT ( clock, reset : IN STD_LOGIC; input: IN STD_LOGIC_VECTOR(7 DOWNTO 0); enter: IN STD_LOGIC; done: OUT STD_LOGIC; output: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END mp; ARCHITECTURE FSMD OF mp IS TYPE state_type IS (s0, s1, s2, s3); SIGNAL state: state_type; SIGNAL X: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Largest: STD_LOGIC_VECTOR(7 DOWNTO 0);

Up2flex.gdf

signal pin number clock Pin_91 Enter Pin_28 Reset Pin_29 aN1 Pin_17 aN10 Pin_6 input(7) Pin_41 bN1 Pin_18 bN10 Pin_7 input(6) Pin_40 cN1 Pin_19 cN10 Pin_8 input(5) Pin_39 dN1 Pin_20 dN10 Pin_9 input(4) Pin_38 eN1 Pin_21 eN10 Pin_11 input(3) Pin_36 fN1 Pin_23 fN10 Pin_12 input(2) Pin_35 gN1 Pin_24 gN10 Pin_13 input(1) Pin_34 pointN100 Pin_25 pointN200 Pin_14 input(0) Pin_33