PDK Standardization

Use of standardized design kit and process flow by all consortium members -> (tracking of releases, documentation, quality assurance – wrrrrr!), Standardization of design kit – work in agreement and close collaboration with Tezzaron – we have to see what will be provided in the PDK release promised by Bob Patti for June, Shall we show some initiative in meantime to look ahead our needs and solutions appropriate to our needs that may be different with respect to ‘industrial’ 3D-IC users Standardization of tools (CAD platform Cadence <-> MicroMagic, verification DRC, LVS, 3DLVS, ERC – there are many ideas and some groups manage to find their way through this bumpy road) Recommendation coming from one group/coordination person (track of release versions, documentation access for downloading current PDK release) Patch working of PDK to satisfy current needs of separate groups in the consortium -> translated to some good software codes realizing goals like LVS, 3DLVS, screening, GDS layer compatibility -> how to put all these efforts under one umbrella -> Shall silicon brokers (metal fill routine was life saving) take this work on themselves (CMP-MOSIS-CMC), Tezzaron job? -> Shall / can we provide effort to follow CERN scheme done for 0.13um IBM process (hire external developer Cadence VCAD)? -> Shall we organize ourselves and provide pdk maintenance within the consortium members?

ISSUES: DFII – OA (OA can be technology independent – good in case Tezzaron provides access to other processes than Chartered), OA is compatible with MicroMagic OA – translation from DFII is painful Distribution of standard digital cells – is ARM rework in agreement with NDA? More?

Many people highlight necessity of standardization and availability of features allowing stable and longer term designs How should we organize ourselves? We talk to Tezzaron to pass our ideas and discuss what Tezzaron is planning to provide to us. Discuss in meantime within the consortium Bring all discussion to more concrete results when we meet at VIPS in ~1 month Who is willing to commit to / have resources to / contribute to shared work ? When? How? How many runs/year shall we think about – to provide smooth design flows, to justify and motivate efforts on the standardized stabilized PDK Which way to go?

The ultimate goal should be to provide a whole standardized package including DBI feature (extremely appealing to the HEP community) – it can be difficult to imagine having that on runs organized by silicon brokers (special operation and approach to the frame preparation are required) what do the consortium members think about this? Any other ideas??? Needs?