ADC12J4000, TSW14J10, KC105, Dec 4x.

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Presentation transcript:

ADC12J4000, TSW14J10, KC105, Dec 4x

Test Setup: Single tone is given as input to the device. Test conditions: Fs = External 2GHz Fin = 600MHz Dec 4 P54 mode LMK = 1GHz, clock dist mode KC705 Ref clock = 250MHz (/4 for LMK) KC705 Core clock = 125MHz (/8 for LMK) Lane Rate = 5G V2p8 firmware

On ADC GUI, load the values as shown below

On ADC GUI, load the values as shown below

On ADC GUI, load the Preset 0 Frequency value as shown below

In Low Level View tab, set LMK04828 address 0x110 to 0x04 to set KC705 REFCLK = 250MHz

In Low Level View tab, set LMK04828 address 0x100 to 0x08 for KC705 Core CLK = 125MHz

Open HSDCD Pro, select “ADC12J4000_D4_DDR”, Enter “500G” for ADC Output Data Rate