Unit -4 Introduction to Embedded Systems Tuesday.

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Presentation transcript:

Unit -4 Introduction to Embedded Systems Tuesday

Unit – 4 : Introduction To Embedded Systems Embedded systems overview Design challenge Processor technology IC technology Design Technology Trade-offs.

3 IC technology Every processor must eventually be implemented on an Integrated Circuits (ICs) A number of different processes exist to build semiconductors, the most popular of which is Complementary Metal Oxide Semiconductor (CMOS) IC technology involves the manner in which a digital (gate-level) implementation is mapped onto an IC – IC: Integrated circuit, or “chip” – It is a semiconductor device consisting of a set of connected transistors and other devices

4 IC technology IC technologies differ in their customization to a design – IC’s consist of numerous layers (perhaps 10 or more) – Bottom layers form the transistors – The middle layers form the logic components – Top layers connect these components with wires IC technologies differ with respect to who builds each layer and when sourcedrain channel oxide gate Silicon substrate IC package IC

5 IC technology Three types of IC technologies – Full-custom/VLSI – Semi-custom ASIC (gate array and standard cell) – PLD (Programmable Logic Device) Field Programmable Gate Array (FPGA) Note : IC technology is independent from processor technology, i.e., any type of processor can be mapped to any type of IC technology

6 Full-custom/VLSI IC Technology All layers are optimized for an embedded system’s particular digital implementation – Placing transistors to minimize interconnect length – Sizing transistors to optimize signal transmissions – Routing wires among the transistors Benefits – Excellent performance, small size, low power Drawbacks – Very High NRE cost (e.g., $300k), long time-to-market Used only in high volume or extremely performance critical applications

7 Semi-custom IC Technology Lower layers are fully or partially built – Designers are left with routing of wires and maybe placing some blocks In a standard cell ASIC technology, logic level cells (AND gate, or AND – OR-Invert) are predesigned Benefits – Good performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k) Drawbacks – Still require weeks to months to develop

PLD (Programmable Logic Device) All layers already exist – Designers can purchase an IC before finishing design – Connections on the IC are either created or destroyed to implement desired functionality – Field-Programmable Gate Array (FPGA) very popular Simple PLD : PLA;Complex PLD : FPGA Benefits – Low NRE costs, almost instant IC availability, well suited for rapid prototyping Drawbacks – Bigger, expensive (perhaps $30 per unit), power hungry, slower

9 Moore’s law The most important trend in embedded systems – Predicted in 1965 by Intel co-founder Gordon Moore IC transistor capacity has doubled roughly every 18 months for the past several decades 10,000 1, Logic transistors per chip (in millions) Note: logarithmic scale

10 Graphical illustration of Moore’s law Leading edge chip in ,000 transistors Leading edge chip in ,000,000 transistors Something that doubles frequently grows more quickly than most people realize! – A 2002 chip can hold about 15, chips (15,000 MPUs) inside itself May be an 8-bit MPU